Real Time Fault Site Isolation of Front-End Defects in ULSI-ESRAM Utilizing In-Line Passive Voltage Contrast Inspection

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2002, Pages 591-598

  Patterson, Oliver D ^a   Drown, Jennifer L ^a   Crevasse, Brian D ^a   Salah, Ahmed ^a   Harris, Keiko K ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FOCUSED ION BEAMS (FIB); PASSIVE VOLTAGE CONTRAST (PVC);

COMPUTER SOFTWARE; ELECTRIC POTENTIAL; FAILURE ANALYSIS; ION BEAMS; SCANNING ELECTRON MICROSCOPY; SILICON WAFERS; TRANSMISSION ELECTRON MICROSCOPY; ULSI CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 0242516890     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Barton, E. Cole Jr, "Advanced Failure Analysis Techniques For Defect Localization," IRPS Conference Tutorial Notes, Topic 8.0. (1997)
2. A. V. S. Satya, "Microelectronic Test Structures for Rapid Automated Contactless Inline Defect Inspection", IEEE Trans. Semi. Manuf., Vol. 10, No. 3, 384-9 (1997)
3. K. Weiner, T. Henry, A. Satya, G. Verman, R. Wu, O. Patterson, B. Crevasse, K. Cauffman, W. Cauffman, "Defect Management for 300mm and 130mm Technologies Part 3 : Another Day, Another Yield Learning Cycle," Yield Management Solutions, Vol. 4, Iss. 1, 15-27 (Winter 2002)
4. V. Liang, H. Sur, S. Bothra, "Passive Voltage Contrast Technique for Rapid In-line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology," Proceedings of ISTFA, 221-5 (1998)
5. A. Nishikawa, N. Kato, Y. Kohno, N. Miura, M. Shimizu, "An Application of Passive Voltage Contrast (PVC) to Failure Analysis of CMOS LSI Using Secondary Electron Collection," Proceedings of ISTFA, 239-243 (1999)
6. S. Bothra, H. Sur, V. Liang, "A New Failure Mechanism by Corrosion of Tungsten in a Tungsten Plug Process," Proceedings of ISTFA, 150-156 (1998)
7. P. Mullenix, J. Zalnoski, A. J. Kasten, "Limited Yield Estimation for Visual Defect Sources", Trans. On Semiconductor Manufacturing, vol. 10, no. 1, 17-23 (1997)
8. O. D. Patterson, M. H. Hansen, "The Impact of Tolerance on Kill Ratio Estimation for Memory", Proceedings of ASMC, 175-180 (2000)