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Volumn 41, Issue 4, 2006, Pages 781-790

AES-based security coprocessor IC in 0.18-μm CMOS with resistance to differential power analysis side-channel attacks

Author keywords

Advanced Encryption Standard (AES); Biometrics; Cryptography; Differential power analysis; Security; Side channel attacks

Indexed keywords

ADVANCED ENCRYPTION STANDARD (AES); BIOMETRICS; DIFFERENTIAL POWER ANALYSIS; DIGITAL CMOS GATES; SECURITY;

EID: 33645675518     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870913     Document Type: Conference Paper
Times cited : (149)

References (14)
  • 5
    • 33645692468 scopus 로고    scopus 로고
    • AES-based cryptographic and biometric security coprocessor IC in 0.18-μm CMOS resistant to side-channel power analysis attacks
    • Jun.
    • K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, "AES-based cryptographic and biometric security coprocessor IC in 0.18-μm CMOS resistant to side-channel power analysis attacks," in Symp. VLSI Circuits Dig., Jun. 2005, pp. 216-219.
    • (2005) Symp. VLSI Circuits Dig. , pp. 216-219
    • Tiri, K.1    Hwang, D.2    Hodjat, A.3    Lai, B.4    Yang, S.5    Schaumont, P.6    Verbauwhede, I.7
  • 6
    • 0003508558 scopus 로고    scopus 로고
    • [Online]
    • National Institute of Standards and Technology, Advanced Encryption Standard. [Online], Available: http://csrc.nist.gov/publica-tions/fips/fip 197/fips-197.pdf 2001
    • (2001) Advanced Encryption Standard
  • 8
    • 3042604811 scopus 로고    scopus 로고
    • A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
    • Feb.
    • K. Tiri and I. Verbauwhede, "A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation," in Proc. Design Automation and Test in Europe Conf. (DATE), Feb. 2004, pp. 246-251.
    • (2004) Proc. Design Automation and Test in Europe Conf. (DATE) , pp. 246-251
    • Tiri, K.1    Verbauwhede, I.2
  • 9
    • 33645696140 scopus 로고    scopus 로고
    • [Online]
    • International Technology Roadmap for Semiconductors (ITRS), Interconnect. [Online], Available: http://public.itrs.net/Files/2003ITRS/Interconnect2003.pdf 2003
    • (2003) Interconnect
  • 11
    • 3142699811 scopus 로고    scopus 로고
    • A 10-Gbps full-AES design with a twisted BDD S-box architecture
    • Jul.
    • S. Morioka and A. Satoh, "A 10-Gbps full-AES design with a twisted BDD S-box architecture," IEEE Trans. Veiy Large Scale Integr. (VLSI) Syst., vol. 12, no. 7, pp. 686-691, Jul. 2004.
    • (2004) IEEE Trans. Veiy Large Scale Integr. (VLSI) Syst. , vol.12 , Issue.7 , pp. 686-691
    • Morioka, S.1    Satoh, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.