Enhanced CMOS performances using substrate strained-SiGe and mechanical strained-Si technology

IEEE Electron Device Letters

Volumn 27, Issue 1, 2006, Pages 46-48

  Wu, San Lein ^a   Lin, Yu Min ^b   Chang, Shoou Jinn ^b   Lu, Shin Chi ^c   Chen, Pang Shiu ^c   Liu, Chee Wee ^c  

^a Department of Electronics Engineering ^*  (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^c INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

CMOS; Compressive stress; Mechanical tensile stress

Indexed keywords

COMPRESSIVE STRESS; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SUBSTRATES; TENSILE STRESS; TRANSCONDUCTANCE;

DRIVE CURRENT; MECHANICAL TENSILE STRESS; NITRIDE CAPPING LAYER;

CMOS INTEGRATED CIRCUITS;

EID: 33645469632     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.860888     Document Type: Article

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