High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 854-859

  Van Der Plas, G ^a   Badaroglu, M ^a,b   Vandersteen, G ^a,c   Dobrovolny, P ^a   Wambacq, P ^a,c   Donnay, S ^a   Gielen, G ^b   De Man, H ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

Model order reduction; Modeling; Substrate noise

Indexed keywords

COMPUTER SIMULATION; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; ERROR ANALYSIS; MATHEMATICAL MODELS; NATURAL FREQUENCIES; NETWORKS (CIRCUITS); PRINTED CIRCUIT DESIGN; PROBLEM SOLVING; SPURIOUS SIGNAL NOISE; WAVEFORM ANALYSIS;

ANALOG CIRCUITS; MODEL ORDER REDUCTION; MODELING; SUBSTRATE NOISE;

DIGITAL CIRCUITS;

EID: 4444245184     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996794     Document Type: Conference Paper

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