-
2
-
-
0035274550
-
Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver
-
Mar.
-
M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee, and B. A. Wooley, "Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver," IEEE J. Solid-State Circuits, vol. 36, pp. 473-485, Mar. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 473-485
-
-
Xu, M.1
Su, D.K.2
Shaeffer, D.K.3
Lee, T.H.4
Wooley, B.A.5
-
3
-
-
0027576336
-
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
-
Apr.
-
D. K. Su. M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 28, pp. 420-430, Apr. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 420-430
-
-
Su, D.K.1
Loinaz, M.J.2
Masui, S.3
Wooley, B.A.4
-
4
-
-
0033703261
-
A scalable substrate noise coupling model for design of mixed signal IC's
-
June
-
A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, "A scalable substrate noise coupling model for design of mixed signal IC's," IEEE J. Solid-State Circuits, vol. 35, pp. 895-904, June 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 895-904
-
-
Samavedam, A.1
Sadate, A.2
Mayaram, K.3
Fiez, T.S.4
-
5
-
-
0035274508
-
Physical design guides for substrate noise reduction in cmos digital circuits
-
Mar.
-
M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, "Physical design guides for substrate noise reduction in cmos digital circuits." IEEE J. Solid-State Circuits, vol. 36, pp. 539-549, Mar. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 539-549
-
-
Nagata, M.1
Nagai, J.2
Hijikata, K.3
Morie, T.4
Iwata, A.5
-
6
-
-
0043061810
-
Enabling high-performance logic mixed-signal system-on-chip (SoC) in high-performance logic CMOS technology
-
L. M. Franca-Neto, P. Pardy, M. P. Ly, R. Rangel, S. Suthar, T. Syed, B. Bloechel, S. Lee, C. Burnett, D. Cho, D. Kau, A. Fazio, and K. Soumyanath, "Enabling high-performance logic mixed-signal system-on-chip (SoC) in high-performance logic CMOS technology," in Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 164-167.
-
(2002)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 164-167
-
-
Franca-Neto, L.M.1
Pardy, P.2
Ly, M.P.3
Rangel, R.4
Suthar, S.5
Syed, T.6
Bloechel, B.7
Lee, S.8
Burnett, C.9
Cho, D.10
Kau, D.11
Fazio, A.12
Soumyanath, K.13
-
7
-
-
0036857246
-
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal IC's with synchronous digital circuits
-
Nov.
-
M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, M. Engels, G. Gielen, and H. De Man, "Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal IC's with synchronous digital circuits," IEEE J. Solid-State Circuits, vol. 37, pp. 1383-1395, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 1383-1395
-
-
Badaroglu, M.1
Van Heijningen, M.2
Gravot, V.3
Compiet, J.4
Donnay, S.5
Engels, M.6
Gielen, G.7
De Man, H.8
-
8
-
-
0029227539
-
A methodology for rapid estimation of substrate-coupled switching noise
-
S. Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, "A methodology for rapid estimation of substrate-coupled switching noise," in Proc. Custom Integrated Circuits Conf., 1995, pp. 7.4.1-7.4.4.
-
(1995)
Proc. Custom Integrated Circuits Conf.
, pp. 741-744
-
-
Mitra, S.1
Rutenbar, R.A.2
Carley, L.R.3
Allstot, D.J.4
-
9
-
-
0035058164
-
Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification
-
M. van Heijningen, M. Badaroglu, S. Donnay, H. De Man, G. Gielen, M. Engels, and I. Bolsens, "Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 342-343.
-
(2001)
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 342-343
-
-
Van Heijningen, M.1
Badaroglu, M.2
Donnay, S.3
De Man, H.4
Gielen, G.5
Engels, M.6
Bolsens, I.7
-
10
-
-
0036917746
-
A Bluetooth radio in 0.18-μm CMOS
-
Dec.
-
P. T. M. van Zeijl, J. W. Eikenbroek, P. P. Vervoort, S. Setty, J. Tangenberg, G. Shipton, E. Kooistra, I. Keekstra, D. Belot, K. Visser, E. Bosma, and S. C. Blaakmeer, "A Bluetooth radio in 0.18-μm CMOS." IEEE J. Solid-State Circuits, vol. 37, pp. 1679-1687, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 1679-1687
-
-
Van Zeijl, P.T.M.1
Eikenbroek, J.W.2
Vervoort, P.P.3
Setty, S.4
Tangenberg, J.5
Shipton, G.6
Kooistra, E.7
Keekstra, I.8
Belot, D.9
Visser, K.10
Bosma, E.11
Blaakmeer, S.C.12
-
12
-
-
0038126914
-
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies
-
M. Badaroglu, S. Donnay, H. De Man, Y. Zinzius, G. Gielen, T. Fondén, and S. Signell, "Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies." in Proc. Eur. Solid-State Circuits Conf., 2002, pp. 291-294.
-
(2002)
Proc. Eur. Solid-State Circuits Conf.
, pp. 291-294
-
-
Badaroglu, M.1
Donnay, S.2
De Man, H.3
Zinzius, Y.4
Gielen, G.5
Fondén, T.6
Signell, S.7
-
13
-
-
0035506207
-
80 MB/s QPSK and 72 Mb/s 64-QAM, flexible and scalable digital OFDM transceiver ASIC's for wireless local area networks in the 5 GHz band
-
Nov.
-
W. Eberle, V. Derudder, G. Vanwijnsberghe, M. Vergara, L. Deneire, L. Van der Perre, M. Engels, I. Bolsens, and H. De Man, "80 MB/s QPSK and 72 Mb/s 64-QAM, flexible and scalable digital OFDM transceiver ASIC's for wireless local area networks in the 5 GHz band." IEEE J. Solid-State Circuits, vol. 36, pp. 1829-1838, Nov. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1829-1838
-
-
Eberle, W.1
Derudder, V.2
Vanwijnsberghe, G.3
Vergara, M.4
Deneire, L.5
Van der Perre, L.6
Engels, M.7
Bolsens, I.8
De Man, H.9
-
14
-
-
84893711030
-
Implementation of an efficient lattice digital ladder filter for up/down conversion in an OFDM-WLAN system
-
S. Signell, T. Fonden, M. Badaroglu, and S. Donnay, "Implementation of an efficient lattice digital ladder filter for up/down conversion in an OFDM-WLAN system," in Proc. Eur. Solid-State Circuits Conf., 2001, pp. 480-483.
-
(2001)
Proc. Eur. Solid-State Circuits Conf.
, pp. 480-483
-
-
Signell, S.1
Fonden, T.2
Badaroglu, M.3
Donnay, S.4
-
15
-
-
0036045371
-
A 8-bit 200-MS/s interpolating/averaging CMOS A/D converter
-
J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert, and G. Gielen, "A 8-bit 200-MS/s interpolating/averaging CMOS A/D converter," in Proc. Custom Integrated Circuits Conf., 2002, pp. 445-448.
-
(2002)
Proc. Custom Integrated Circuits Conf.
, pp. 445-448
-
-
Vandenbussche, J.1
Uyttenhove, K.2
Lauwers, E.3
Steyaert, M.4
Gielen, G.5
-
16
-
-
0034228948
-
Analysis and experimental verification of digital substrate noise generation for EPI-type substrates
-
July
-
M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Analysis and experimental verification of digital substrate noise generation for EPI-type substrates." IEEE J. Solid-State Circuits, vol. 35, pp. 1002-1008, July 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1002-1008
-
-
Van Heijningen, M.1
Compiet, J.2
Wambacq, P.3
Donnay, S.4
Engels, M.5
Bolsens, I.6
-
17
-
-
0033700093
-
High-level simulation of substrate noise generation including power supply noise coupling
-
June
-
M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, "High-Level simulation of substrate noise generation including power supply noise coupling." in Proc. IEEE/ACM Design Automation Conf., June 2000, pp. 446-451.
-
(2000)
Proc. IEEE/ACM Design Automation Conf.
, pp. 446-451
-
-
Van Heijningen, M.1
Badaroglu, M.2
Donnay, S.3
Engels, M.4
Bolsens, I.5
-
18
-
-
0038803829
-
-
[Online]
-
SubstrateStorm from Cadence [Online]. Available: http://www.cadence.com/datasheets/substratestorm.html
-
-
-
-
19
-
-
0036054409
-
Clock tree optimization in synchronous CNMOS circuits for substrate noise reduction using folding of supply currents
-
June
-
M. Badaroglu, K. Tiri, S. Donnay, P. Wambacq, I. Verbauwhede, G. Gielen, and H. De Man, "Clock tree optimization in synchronous CNMOS circuits for substrate noise reduction using folding of supply currents," in Proc. IEEE/ACM Design Automation Conf., June 2002, pp. 399-405.
-
(2002)
Proc. IEEE/ACM Design Automation Conf.
, pp. 399-405
-
-
Badaroglu, M.1
Tiri, K.2
Donnay, S.3
Wambacq, P.4
Verbauwhede, I.5
Gielen, G.6
De Man, H.7
|