Energy-efficient thread-level speculation

IEEE Micro

Volumn 26, Issue 1, 2006, Pages 80-91

  Renau, Jose ^a   Strauss, Karin ^b   Ceze, Luis ^b   Liu, Wei ^b   Sarangi, Smruti R ^b   Tuck, James ^b   Torrellas, Josep ^b  

^a University of California Santa Cruz   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAM COMPILERS; PROGRAM PROCESSORS;

CHIP MULTIPROCESSORS; SPECULATIVE TASK-LEVEL PARALLELISM; THREAD-LEVEL SPECULATION;

PARALLEL PROCESSING SYSTEMS;

EID: 33644916639     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2006.11     Document Type: Article

References (16)

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