-
1
-
-
0022985546
-
"A novel high-speed, 5-volt programming EPROM structure"
-
A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu, "A novel high-speed, 5-volt programming EPROM structure," in IEDM Tech. Dig., 1986, pp. 584-587.
-
(1986)
IEDM Tech. Dig.
, pp. 584-587
-
-
Wu, A.T.1
Chan, T.Y.2
Ko, P.K.3
Hu, C.4
-
2
-
-
0024870476
-
"A new Flash erase EEPROM cell with a sidewall select-gate on its source side"
-
K. Naruke, S. Yamada, E. Obi, S. Taguchi, and M. Wada, "A new Flash erase EEPROM cell with a sidewall select-gate on its source side," in IEDM Tech. Dig., 1989, pp. 603-606.
-
(1989)
IEDM Tech. Dig.
, pp. 603-606
-
-
Naruke, K.1
Yamada, S.2
Obi, E.3
Taguchi, S.4
Wada, M.5
-
3
-
-
33244464567
-
"Flash Memory Cell with Self-Aligned Gates and Fabrication Process"
-
Sep. 18
-
C.-F. Chen, "Flash Memory Cell with Self-Aligned Gates and Fabrication Process," U.S. Patent 6 291 297 B1, Sep. 18, 2001.
-
(2001)
U.S. Patent 6 291 297 B1
-
-
Chen, C.-F.1
-
4
-
-
0000941771
-
"Memory architecture and related issues"
-
P. Cappelletti et al., Eds. Norwell, MA: Kluwer
-
M. Branchetti, G. Campardo, S. Commodaro, S. Ghezzi, A. Ghilardelli, C. Golla, I. Martines, M. Maccarrone, R. Micheloni, M. Zammattio, and S. Zanardi et al., "Memory architecture and related issues," in Flash Memories, P. Cappelletti et al., Eds. Norwell, MA: Kluwer, 1999, pp. 264-266.
-
(1999)
Flash Memories
, pp. 264-266
-
-
Branchetti, M.1
Campardo, G.2
Commodaro, S.3
Ghezzi, S.4
Ghilardelli, A.5
Golla, C.6
Martines, I.7
Maccarrone, M.8
Micheloni, R.9
Zammattio, M.10
Zanardi, S.11
-
5
-
-
0028496775
-
"A 5 V-compatible Flash EEPROM cell with microsecond programming time for embedded memory applications"
-
Sep
-
J. Van Houdt, D. Wellekens, L. Faraone, L. Haspeslagh, and L. Deferm, "A 5 V-compatible Flash EEPROM cell with microsecond programming time for embedded memory applications," IEEE Trans. Compon., Packag., Manufact. Technol. A, vol. 17, pp. 380-389, Sep. 1994.
-
(1994)
IEEE Trans. Compon., Packag., Manufact. Technol. A
, vol.17
, pp. 380-389
-
-
Van Houdt, J.1
Wellekens, D.2
Faraone, L.3
Haspeslagh, L.4
Deferm, L.5
-
6
-
-
0029406379
-
"Write/erase degradation in source side injection Flash EEPROM's: Characterization techniques and wearout mechanisms"
-
Nov
-
D. Wellekens, J. Van Houdt, L. Faraone, G. Groeseneken, and H. E. Maes, "Write/erase degradation in source side injection Flash EEPROM's: Characterization techniques and wearout mechanisms," IEEE Trans. Electron Dev., vol. 42, no. 11, pp. 1992-1998, Nov. 1995.
-
(1995)
IEEE Trans. Electron Dev.
, vol.42
, Issue.11
, pp. 1992-1998
-
-
Wellekens, D.1
Van Houdt, J.2
Faraone, L.3
Groeseneken, G.4
Maes, H.E.5
-
7
-
-
0032122853
-
"Analysis of enhanced hot-carrier effects in scaled Flash memory devices"
-
Jul
-
C. Chen, Z.-Z. Liu, and T.-P. Ma, "Analysis of enhanced hot-carrier effects in scaled Flash memory devices," IEEE Trans. Electron Devices, vol. 45, no. 7, pp. 1524-1530, Jul. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, Issue.7
, pp. 1524-1530
-
-
Chen, C.1
Liu, Z.-Z.2
Ma, T.-P.3
-
8
-
-
0002646843
-
"Flash memory reliability"
-
P. Cappelletti et al., Eds. Norwell, MA: Kluwer
-
P. Cappelletti and A. Modelli et al., "Flash memory reliability," in Flash Memories, P. Cappelletti et al., Eds. Norwell, MA: Kluwer, 1999, pp. 417-418.
-
(1999)
Flash Memories
, pp. 417-418
-
-
Cappelletti, P.1
Modelli, A.2
-
9
-
-
84949750269
-
"Data retention failure in NOR Flash memory cells"
-
W. H. Lee, D.-K. Lee, T.-M. Park, K.-S. Kim, K.-O. Ahn, and K. D. Suh, "Data retention failure in NOR Flash memory cells," in Proc. 2001 39th Int. Reliab. Phys. Symp., pp. 57-60.
-
Proc. 2001 39th Int. Reliab. Phys. Symp.
, pp. 57-60
-
-
Lee, W.H.1
Lee, D.-K.2
Park, T.-M.3
Kim, K.-S.4
Ahn, K.-O.5
Suh, K.D.6
-
10
-
-
33244461795
-
"A novel sphere-based statistical model for local oxide thinning induced gate oxide breakdown"
-
H.-T. Huang and M.-J. Chen, "A novel sphere-based statistical model for local oxide thinning induced gate oxide breakdown," in Proc. 2000 Int. Conf. Solid State Devices and Mater., pp. 246-247.
-
Proc. 2000 Int. Conf. Solid State Devices and Mater.
, pp. 246-247
-
-
Huang, H.-T.1
Chen, M.-J.2
-
11
-
-
33244485923
-
"Method of programming a Flash EEPROM memory cell array optimized for low power consumption"
-
Mar. 28
-
J. Van Houdt, L. Haspeslagh, L. Deferm, G. Groeseneken, and H. E. Maes, "Method of programming a Flash EEPROM memory cell array optimized for low power consumption," U.S. Patent 6 044 015, Mar. 28, 2000.
-
(2000)
U.S. Patent 6 044 015
-
-
Van Houdt, J.1
Haspeslagh, L.2
Deferm, L.3
Groeseneken, G.4
Maes, H.E.5
-
12
-
-
0027803216
-
2PROM cell for embedded memory applications"
-
Dec
-
2PROM cell for embedded memory applications," IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2255-2263, Dec. 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, Issue.12
, pp. 2255-2263
-
-
Van Houdt, J.1
Haspeslagh, L.2
Wellekens, D.3
Deferm, L.4
Groeseneken, G.5
Maes, H.E.6
-
13
-
-
1842832726
-
"Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells"
-
C. Y.-S. Cho and M.-J. Chen, "Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells," Solid State Electron., vol. 48, pp. 1189-1195, 2004.
-
(2004)
Solid State Electron.
, vol.48
, pp. 1189-1195
-
-
Cho, C.Y.-S.1
Chen, M.-J.2
-
14
-
-
0022751486
-
"A quantitative model for the conduction in oxides thermally grown from polycrystalline silicon"
-
Jul
-
G. Groeseneken and H. E. Maes, "A quantitative model for the conduction in oxides thermally grown from polycrystalline silicon," IEEE Trans. Electron Devices, vol. ED-33, no. 7, pp. 1028-1042, Jul. 1986.
-
(1986)
IEEE Trans. Electron Devices
, vol.ED-33
, Issue.7
, pp. 1028-1042
-
-
Groeseneken, G.1
Maes, H.E.2
-
16
-
-
0029342236
-
"An analytical model for the optimization of source-side injection flash EEPROM devices"
-
Oct
-
J. V. Houdt, G. Groeseneken, and H. E. Maes, "An analytical model for the optimization of source-side injection flash EEPROM devices," IEEE Trans. Electron Devices, vol. 42, no. 10, pp. 1314-1320, Oct. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, Issue.10
, pp. 1314-1320
-
-
Houdt, J.V.1
Groeseneken, G.2
Maes, H.E.3
-
17
-
-
0028602570
-
"A novel high density contactless flash memory array using split-gate source-side injection cell for 5 V-only application"
-
Y. Ma, C. S. Pang, J. Pathak, S. C. Tsao, C. F. Chang, Y. Yamauchi, and M. Yoshimi, "A novel high density contactless flash memory array using split-gate source-side injection cell for 5 V-only application," in Symp. VLSI Tech. Dig., vol. 5A, pp. 49-50.
-
Symp. VLSI Tech. Dig.
, vol.5 A
, pp. 49-50
-
-
Ma, Y.1
Pang, C.S.2
Pathak, J.3
Tsao, S.C.4
Chang, C.F.5
Yamauchi, Y.6
Yoshimi, M.7
-
18
-
-
0034217293
-
"The impacts of control gate voltage on the cycling endurance of split gate flash memory"
-
Apr
-
K.-C. Huang, Y.-K. Fang, D.-N. Yaung, C.-W. Chen, H.-C. Sung, D.-S. Kuo, C. S. Wang, and M.-S. Liang, "The impacts of control gate voltage on the cycling endurance of split gate flash memory," IEEE Electron Device Lett., vol. 21, no. 4, pp. 359-361, Apr. 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, Issue.4
, pp. 359-361
-
-
Huang, K.-C.1
Fang, Y.-K.2
Yaung, D.-N.3
Chen, C.-W.4
Sung, H.-C.5
Kuo, D.-S.6
Wang, C.S.7
Liang, M.-S.8
-
19
-
-
0037560880
-
"An analytical model for optimization of programming efficiency and uniformity of split gate source-side injection Superflash memory"
-
May
-
H. Guan, D. Lee, and G. P. Li, "An analytical model for optimization of programming efficiency and uniformity of split gate source-side injection Superflash memory," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 809-815, May 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.5
, pp. 809-815
-
-
Guan, H.1
Lee, D.2
Li, G.P.3
-
21
-
-
33244456437
-
"Self aligned method of forming a semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges, and a memory array made thereby"
-
Jun. 15
-
G.-C. Chern, "Self aligned method of forming a semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges, and a memory array made thereby," U.S. Patent 6 750 090 B2, Jun. 15, 2004.
-
(2004)
U.S. Patent 6 750 090 B2
-
-
Chern, G.-C.1
-
22
-
-
33244454818
-
"Self aligned method of forming a semiconductor array of non-volatile memory cells"
-
Mar. 16
-
G.-C. M. Chern and C.-S. Su, "Self aligned method of forming a semiconductor array of non-volatile memory cells," U.S. Patent 6 706 592 B2, Mar. 16, 2004.
-
(2004)
U.S. Patent 6 706 592 B2
-
-
Chern, G.-C.M.1
Su, C.-S.2
-
23
-
-
4544236116
-
"Split-gate NAND Flash memory at 120 nm technology node featuring fast programming and erase"
-
C.-Y. Hsu, C.-W. Hung, D. Sung, C.-S. Wu, S. C. Chen, H. H. Kuo, J. Y. Pan, C. L. Chen, I. C. Chuang, V. Huang, C. C. Hsue, D.-T. Fan, J.-C. Lu, C. Y.-S. Cho, K. Tseng, A. Hsu, B. Sheen, P. Tuntasood, and C.-F. Chen, "Split-gate NAND Flash memory at 120 nm technology node featuring fast programming and erase," in Symp. VLSI Tech. Dig., 2004, pp. 78-79.
-
(2004)
Symp. VLSI Tech. Dig.
, pp. 78-79
-
-
Hsu, C.-Y.1
Hung, C.-W.2
Sung, D.3
Wu, C.-S.4
Chen, S.C.5
Kuo, H.H.6
Pan, J.Y.7
Chen, C.L.8
Chuang, I.C.9
Huang, V.10
Hsue, C.C.11
Fan, D.-T.12
Lu, J.-C.13
Cho, C.Y.-S.14
Tseng, K.15
Hsu, A.16
Sheen, B.17
Tuntasood, P.18
Chen, C.-F.19
-
24
-
-
33244489421
-
"Multi-level split gate NAND memory with fast program and erase in 120 nm"
-
H.-H. Kuo, J.-Y. Pan, C.-L. Chen, I.-C. Chuang, S.-C. Chen, C.-Y, Hsu, D. Sung, C.-W. Hung, V. Huang, C.-C. Cho, C.-C. Hsue, D.-T. Fan, J.-C. Lu, K. Tseng, J. Pabustan, S. Wang, A. Hsu, B. Sheen, P. Tuntasood, and C.-F. Chen, "Multi-level split gate NAND memory with fast program and erase in 120 nm," in Proc. 2004 NVSMW, pp. 37-39.
-
Proc. 2004 NVSMW
, pp. 37-39
-
-
Kuo, H.-H.1
Pan, J.-Y.2
Chen, C.-L.3
Chuang, I.-C.4
Chen, S.-C.5
Hsu, C.-Y.6
Sung, D.7
Hung, C.-W.8
Huang, V.9
Cho, C.-C.10
Hsue, C.-C.11
Fan, D.-T.12
Lu, J.-C.13
Tseng, K.14
Pabustan, J.15
Wang, S.16
Hsu, A.17
Sheen, B.18
Tuntasood, P.19
Chen, C.-F.20
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