Analysis of enhanced hot-carrier effects in scaled flash memory devices

IEEE Transactions on Electron Devices

Volumn 45, Issue 7, 1998, Pages 1524-1530

  Chen, Chun ^a   Liu, Zhi Zheng ^a   Ma, T P ^a  

^a Yale University   (United States)

Author keywords

CMOS; Flash memory; Hot carrier effects; Scaling

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRIC CURRENTS; HOT CARRIERS; RELIABILITY;

FLASH MEMORY;

CMOS INTEGRATED CIRCUITS;

EID: 0032122853     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.701484     Document Type: Article

References (13)

1. H. Onoda, Y. Kunori, S. Kobayashi, M. Ohi, A. Fukumoto, N. Ajika, and H. Miyoshi, "A novel cell structure suitable for a 3-V operation, sector erase flash memory," in IEDM Tech. Dig., 1992, pp. 599-602.
2. S. Hadded, C. Chang, A. Wang, J. Bustillo, J. Lien, T. Montalvo, and M. V. Buskirk, "An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell," IEEE Electron Device Lett., vol. 11, pp. 514-516, Nov. 1990.
3. T. C. Ong, A. Fazio, N. Mielke, S. Pan, N. Righos, G. Atwood, and S. Lai, "Erratic erase in ETOX flash memory array," in IEEE VLSI Technol. Symp., 1993, pp. 83-84.
4. K. T. San, C. Kaya, and T. P. Ma, "Effects of erase source bias on flash EPROM device reliability," IEEE Trans. Electron Devices, vol. 42, pp. 150-159, Jan. 1995.
5. J. Chen, J. Hsu, S. Luan, Y. Tang, D. Liu, S. Haddad, C. Chang, S. Longcor, and J. Lien, "Short channel enhanced degradation during discharge of flash EEPROM memory cell," in IEDM Tech. Dig., 1995, pp. 331-334.
6. C. Chen and T. P. Ma, "Direct lateral profiling of both oxide charge and interface traps in thin gate MOSFET devices," in IEEE VLSI Technol. Symp., 1996, pp. 230-231.
7. "Lateral distributions of erase-induced hole trapping and interface traps in flash EPROM/NMOSFET devices," in Semicond. Interface Specialists Conf., Dec. 1996, P. 1.4.
8. C. Chen, Z. Liu, and T. P. Ma, "Enhanced hot-carrier effects in scaled flash memory devices," in Int. Symp. VLSI Technol., Syst., andApplicat., June 1997, pp. 162-166.
9. C. Chen and T. P. Ma, "Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET' s,"IEEE Trans. Electron Devices, vol. 45, pp. 512-520, Feb. 1998.
10. M. Tsuchiaki, H. Hara, T. Morimoto, and H. Iwai, "A new charge pumping method for determining the spatial distribution of hot-carrierinduced fixed charge in p-MOSFET's," in IEEE Trans. Electron Devices, vol. 40, pp. 1768-1778, Oct. 1993.
11. J. S. Witters, G. Groeseneken, and H. E. Maes, "Degradation of tunneloxide floating-gate EEPROM devices and the correlation with high field-current-induced degradation of thin gate oxides," IEEE Trans. Electron Devices, vol. 36, pp. 1663-1682, Sept. 1989.
12. W. Weber, M. Brox, R. Thewes, and N. S. Saks, "Hot-hole-induced negative oxide charges in n-MOSFET's," IEEE Trans. Electron Devices, vol. 42, pp. 1473-1480, Aug. 1995.
13. C. Chen and T. P. Ma, "Comparison of GIDL-induced degradation near graded and abrupt junctions in flash EPROM/NMOSFET devices," presented at IEEE Nonvolatile Memory Workshop, Feb. 1997.