Impacts of control gate voltage on the cycling endurance of split gate flash memory

IEEE Electron Device Letters

Volumn 21, Issue 7, 2000, Pages 359-361

  Huang, Kuo Ching ^a   Fang, Yean Kuen ^a   Yaung, Dun Nian ^a   Chen, Chii Wen ^b   Sung, Hung Cheng ^c   Kuo, Di Son ^c   Wang, Chung S ^c   Liang, Mong Song ^c  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b MINGHSIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; POLYSILICON; PROM; VOLTAGE CONTROL;

CONTROL GATE VOLTAGE; CURRENT DEGRADATION; CYCLING ENDURANCE; SPLIT GATE FLASH MEMORY;

FLASH MEMORY;

EID: 0034217293     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.847380     Document Type: Article

References (9)

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