Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 78-79

  Hsu, Cheng Yuan ^a   Hung, Chi Wei ^a   Sung, Da ^a   Wu, Chi Shan ^a   Chen, S C ^a   Kuo, H H ^a   Pan, J Y ^a   Chen, C L ^a   Chuang, I C ^a   Huang, Vincent ^a   Hsue, C C ^a   Fan, Der Tsyr ^b   Lu, Jung Chang ^b   Cho, Caleb Y S ^b   Tseng, Kevin ^b   Hsu, Annie ^c   Sheen, Ben ^c   Tuntasood, Prateep ^c   Chen, Chiou Feng ^b  

^a POWERCHIP TECHNOLOGY CORPORATION   (Taiwan)

^b Actrans System Inc   (Taiwan)

^c Actrans System Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; GATES (TRANSISTOR); NANOTECHNOLOGY; PROCESS CONTROL; SPECIFICATIONS; THROUGHPUT;

CONTROL GATE (CG); COUPLING RATIO; NAND FLASH MEMORY; SELECT GATE (SG);

FLASH MEMORY;

EID: 4544236116     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Schmizu et al, IEDM Tech. Dig., p271, 1997
2. D.C. Kim et al, IEDM Tech. Dig., p919, 2002
3. S. Kianian et al, Symp. VLSI Tech.,p71, 1994
4. C.-F. Chen, U.S. Patent 6291297 B1, Sep. 18, 2001.
5. C.-F. Chen et al, U.S. Patent pending.