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Volumn 83, Issue 3, 2006, Pages 460-462

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

Author keywords

Boron penetration; Charge trapping; High temperature annealing; Interface trap density; Mechanical stress; Polysilicon capping layer; TiN; Transistor channel length

Indexed keywords

BORON; DIELECTRIC MATERIALS; ELECTRIC CHARGE; MOSFET DEVICES; POLYSILICON; TITANIUM NITRIDE;

EID: 33244483892     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.11.010     Document Type: Article
Times cited : (16)

References (7)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.