Accurate SPICE models for CMOS analog radiation-hardness-by-design

IEEE Transactions on Nuclear Science

Volumn 52, Issue 6, 2005, Pages 2542-2549

  Champion, Corbin L ^a,b,c   La Rue, George S ^a,b  

^a IEEE   (United States)

^b WASHINGTON STATE UNIVERSITY   (United States)

^c TERADYNE INC   (United States)

Author keywords

Analog integrated circuits; Field effect transistor (FET) integrated circuits; Radiation hardening; Semiconductor device modeling

Indexed keywords

ANALOG INTEGRATED CIRCUITS; FIELD-EFFECT TRANSISTOR (FET) INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE MODELING; SPICE MODELS;

CONFORMAL MAPPING; DATA REDUCTION; ELECTRIC RESISTANCE; FABRICATION; FIELD EFFECT TRANSISTORS; MOLECULAR STRUCTURE; RADIATION HARDENING;

CMOS INTEGRATED CIRCUITS;

EID: 33144475055     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.860717     Document Type: Conference Paper

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