Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout

Solid-State Electronics

Volumn 44, Issue 6, 2000, Pages 981-989

  Giraldo, A ^a,b   Paccagnella, A ^a,b   Minzoni, A ^a  

^a UNIVERSITY OF PADOVA   (Italy)

^b SEZIONE DI PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CONFORMAL MAPPING; SEMICONDUCTOR DEVICE MODELS;

GATE-ENCLOSED LAYOUTS;

MOSFET DEVICES;

EID: 0033745487     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(00)00010-1     Document Type: Article

References (20)

1. Anelli G, Campbell M, Del Mastro M, Faccio F, Giraldo A, Heijne E, Jarron P, Kloukinas K, Marchioro A, Moreira P, Snoeys W. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects. IEEE Trans Nucl Sci 1999;46:1630-6.
2. Snoeys W, et al. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstra on a pixel readout chip. Nucl Instru Meth A 2000;439:349-60.
3. Davari B., Dennard R.H., Shahidi G.G. CMOS scaling for high performance and low power - the next ten years. Proc IEEE. 83:1995;595-606.
4. Saks N.S., Ancona M.G., Modolo J.A. Generation of interface states by ionizing radiation in very thin MOS oxides. IEEE Trans Nucl Sci. 33:1986;1185.
5. Acovic A., Hsu C.C.H., Hsia L.C., Aitken J.M. Reduced hot carrier reliability degradation of X-ray irradiated MOSFETs in a 0.25 μm CMOS technology with ultra-thin gate oxides. Solid-State Electron. 36(6):1993;1353-1355.
6. Ceschia M., Paccagnella A., Cester A., Scarpa A., Ghidini G. Stress induced leakage current and radiation induced leakage current on ultra-thin gate oxides. IEEE Trans Nucl Sci. 45:1998;2375-2382.
7. Oldham T.R., Lelis A.J., Boesch H.E., Benedetto J.M., McLean F.B., McGarrity J.M. Post-irradiation effects in field-oxide isolation structures. IEEE Trans Nucl Sci. 34:1987;1184.
8. Ma TP. In: Dressendorfer PV, editors. Ionizing radiation effects in MOS devices and circuits. New York: Wiley, 1989.
9. Dingwall A.G.F., Stricker R.E. C2L: a new high speed high density bulk CMOS technology. IEEE J Solid-State Circuits. 12(4):1977;344-349.
10. Munteanu D., Cristoloveanu S., Hovel H. Circular pseudo-metal oxide semiconductor field effect transistor in silicon-on-insulator. Electrochem Solid State Lett. 2(5):1999;242-243.
11. Van den Bosch A., Steyaert M., Sansen W. A high density matched hexagonal transistor structure in standard CMOS technology for high speed applications. Proc IEEE Int Conf Microelect Test Struct. 12:1999;212-215.
12. Escoffier R, Fichtner W, editors. ISE-TCAD Manuals. Release 5.0. Zurich: ISE, 1998.
13. Kosina H., Langer E., Selberherr S. Device modelling for the 1990s. Microelectron J. 26:1995;217-233.
14. Tsividis YP. Operation and modeling of MOS transistor. New York: McGraw-Hill, 1988.
15. Antognetti P, Massobrio G. Semiconductor device modelling with SPICE. New York: McGraw-Hill, 1988.
16. Foty D. MOSFET modeling with SPICE, principles and practice. Upper Saddle River, NJ: Prentice-Hall, 1997.
17. Giraldo A. Evaluation of deep submicron technologies with radiation tolerant layout for electronics in LHC environments. PhD thesis in physics. University of Padova, 31 December 1998.
18. Jeans JH. The mathematical theory of electricity and magnetism. Cambridge, MA: Cambridge University Press, 1915.
19. Durand E. Électrostatique, Tome II- Problèmes Généraux Conducteurs. Paris: Massonet C, 1966.
20. Feynman RP. The Feynman lectures on physics. vol. 2. Reading, MA: Addison-Wesley, 1964.