A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 2, 2006, Pages 483-495

  Zhong, Guichang ^a,b   Xu, Fan ^a,c   Willson Jr , Alan N ^{a,b,d,e,f,g,h,i}  

^a IEEE   (United States)

^b Engineering IV   (United States)

^c BROADCOM CORPORATION   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e Engineering and Applied Science in the Electrical Engineering Department   (United States)

^f Pentomics Inc   (United States)

^g Eta Kappa Nu ^*  (United States)

^h Society for Industrial and Applied Mathematics   (United States)

ⁱ AMERICAN SOCIETY FOR ENGINEERING EDUCATION   (United States)

Author keywords

ASIC; Cached FFT; Digital signal processor (DSP); Fast Fourier transform (FFT); Inverse FFT (IFFT); Multi processor; Programmable; Reconfigurable; Scalable

Indexed keywords

CACHED-FFT; DIGITAL SIGNAL PROCESSOR (DSP); FAST FOURIER TRANSFORM (FFT); INVERSE FFT (IFFT); MULTI-PROCESSOR; PROGRAMMABLE; RECONFIGURABLE; SCALABLE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATION THEORY; INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS; POWER CONTROL; POWER SUPPLY CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 31644437944     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.862344     Document Type: Article

References (27)

1. N. Tredennick and B. Shimamoto, "Go reconfigure," IEEE Spectrum, vol. 40, no. 12, pp. 26-40, Dec. 2003.
2. J. M. Rabaey, "Reconfigurable processing: The solution to low-power programmable DSP," in Proc. ICASSP, 1997, pp. 275-278.
3. N. Zhang and R. W. Brodersen, "Architectural evaluation of flexible digital signal processing for wireless receivers," in Conf. Rec. 34th Asilomar Conf. Signals, Systems and Computers, vol. 1, 2000, pp. 78-83.
4. B. M. Baas, "A low-power, high-performance, 1024-point FFT processor," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 380-387. Mar. 1999.
5. S. He and M. Torkelson, "Design and implementation of a 1024-point pipeline FFT processor," in Proc. CICC, 1998, pp. 131-134.
6. R. Amirtharajah, T. Xanthopoulos, and A. Chandrakasan, "Power scalable processing using distributed arithmetic," in Proc, ISLPED, Aug. 1999, pp. 170-175.
7. J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series," Math. Comput., vol. 19, pp. 297-301, 1965.
8. G. D. Bergland. "A fast Fourier transform algorithm using base 8 iterations," Math. Comput., vol. 22, pp. 275-279, 1968.
9. A. Kwentus, M. Werter, and A. N. Willson Jr., "A programmable digital filter IC employing multiple processors on a single chip," IEEE Trans. Circuits Syst. Video Technol., vol. 2, no. 2, pp. 231-243, Jun. 1992.
10. M. J. Werter and A. N. Willson Jr., "Automated programming of digital filters for parallel processing implementation." IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 41, no. 4, pp. 285-294, Apr. 1994.
11. D. D. Richard III, "A ring processor for digital filter applications," Master's thesis, Univ. California, Los Angeles, CA, 1999.
12. F. Xu, "On designing high-performance signal processing algorithms for a ring-structured multiprocessor," Ph.D. dissertation, Univ. California. Los Angeles, CA, 2001.
13. F. Xu, G. Zhong, and A. N. Willson Jr., "Analysis and VLSI realization of a blind beamforming algorithm," J. VLSI Signal Process., vol. 40, no. 2, pp. 159-174, Jun. 2005.
14. A. Ahn, S. Nahm, and W. Sung, "VLSI design of a CORDIC-based derotator," in Proc. ISCAS, 1998, pp. 448-452.
15. A. Madisetti, A. Y. Kwentus, and A. N. Willson Jr., "A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range," IEEE J. Solid-State Circuits, vol. 34, no. 8, pp. 1034-1043, Aug. 1999.
16. D. DeCaro, E. Napoli, and A. G. M. Strollo, "Direct digital frequency synthesizer using high-order polynomial approximation," in IEEE ISSCC Dig. Tech. Papers, vol. 1, 2002, pp. 134-135.
17. H. T. Nicolas and H. Samueli, "An analysis of the output spectrum of direct digital frequency synthesizer performance in the presence of finite word length effects," in Proc. 41st. Annu. Symp. Frequency Control, 1987, pp. 495-502.
18. D. Fu, "Efficient synchronization architectures for multimedia communications," Ph.D. dissertation, Univ. California, Los Angeles, CA, 2000.
19. A. Torosyan, D. Fu, and A. N. Willson Jr., "A 300 MHz quadrature direct digital synthesizer/mixer in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 875-887, Jun. 2003.
20. G. Zhong, F. Xu, D. Fu, and A. N. Willson Jr., "An energy-efficient reconfigurable angle-rotator architecture," in Proc. ISCAS, vol. 3, 2004. pp. 661-664.
21. W. W. Smith and J. M. Smith, Handbook of Real-Time Fast Fourier Transforms. Piscataway, NJ: IEEE Press, 1995.
22. J. Kuo, C. Wen, and A. Wu, "Implementation of a programmable 64-2048-point FFT/IFFT processor for OFDM-based communication systems," in Proc. ISCAS, vol. 2, May 2003, pp. 121-124.
23. E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, "A fast single-chip implementation of 8192 compex point FFT," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 300-305, Mar. 1995.
24. A. Wang and A. Chandrakasan, "Energy-aware architecture for a realvalued FFT implementation," in Proc. ISLPED, Aug. 2003, pp. 360-365.
25. FFT Benchmarks, Texas Instruments Inc. [Online], Available: http:// www.ti.com/sc/docs/products/dsp/c6000/benchmarks/64x.htmt#fft
26. Analog Devices. [Online]. Available: http://www.analog.com/processors/ processors/sharc/benchmarks.html
27. FFT Benchmarks, Texas Instruments Inc. [Online]. Available: http://www.ti.com/sc/docs/products/dsp/c6000/benchmarks/62x.htmt#fft