Defect-oriented test scheduling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 3, 2001, Pages 427-438

  Jiang, Wanli ^a,b   Vinnakota, Bapiraju ^c  

^a IEEE   (United States)

^b BOSTON SCIENTIFIC CORPORATION   (United States)

^c University of Minnesota   (United States)

Author keywords

Heuristic sample; Order fault coverage; Test cost scheduling

Indexed keywords

OPTIMAL TEST SCHEDULING; TESTER COMPLEXITY;

ALGORITHMS; COMPUTER SIMULATION; DEFECTS; HEURISTIC METHODS; MATERIALS TESTING; POLYNOMIALS; SCHEDULING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035361795     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.929577     Document Type: Article

References (10)

1. Test economics in the 21st century
2. Scheduling for IC sort and test with preemptiveness via Lagrangian relaxation
3. Scheduling semiconductor device test operations
4. Economic modeling of board test strategies
5. Optimal scheduling of signature analysis for VLSI testing
6. Optimal ordering of analog integrated circuit tests to minimize test time
7. Minimizing production test time to detect faults in analog circuits