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Volumn 2, Issue , 2001, Pages 1021-1025

Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling

Author keywords

[No Author keywords available]

Indexed keywords

CELL LIBRARY; CIRCUIT PERFORMANCE; CLOCK BUFFER; CLOCK SIGNAL; CRITICAL DATA; FUNCTIONAL BLOCK; FUNCTIONAL UNITS; HIGH PERFORMANCE PROCESSORS; HIGH SPEED SYSTEMS; HIGH-PERFORMANCE MICROPROCESSORS; INDUSTRIAL CIRCUITS; NON-ZERO CLOCK SKEW SCHEDULING; SOFTWARE TOOL; SPEED CHARACTERISTICS; SPEED ENHANCEMENT; TIMING CONSTRAINTS; TIMING MARGIN;

EID: 3142663573     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (16)
  • 2
    • 0022701144 scopus 로고
    • Design and analysis for a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI
    • April
    • E. G. Friedman and S. Powell, "Design and Analysis for a Hierarchical Clock Distribution System for Synchronous Standard Cell/macrocell VLSI, " IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 2, pp. 240-246, April 1986.
    • (1986) IEEE Journal of Solid-state Circuits , vol.SC-21 , Issue.2 , pp. 240-246
    • Friedman, E.G.1    Powell, S.2
  • 3
    • 0022953369 scopus 로고
    • A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ULSI and WSI circuits
    • October
    • H. B. Bakoglou, J. T. Walker, and J. D. Meindl, "A Symmetric Clock-Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits, " Proceedings of the IEEE International Conference on Computer Design, pp. 118-122, October 1986.
    • (1986) Proceedings of the IEEE International Conference on Computer Design , pp. 118-122
    • Bakoglou, H.B.1    Walker, J.T.2    Meindl, J.D.3
  • 8
    • 0025464163 scopus 로고
    • Clock skew optimization
    • July
    • J. P. Fishburn, "Clock Skew Optimization, " IEEE Transactions on Computers, Vol. 39, No. 7, pp. 945-951, July 1990.
    • (1990) IEEE Transactions on Computers , vol.39 , Issue.7 , pp. 945-951
    • Fishburn, J.P.1
  • 9
    • 0030167885 scopus 로고    scopus 로고
    • Design methodology for synthesizing clock distribution networks exploiting non-zero clock skew
    • June
    • J. L. Neves and E. G. Friedman, "Design Methodology for Synthesizing Clock Distribution Networks Exploiting Non-Zero Clock Skew, " IEEE Transactions on VLSI Systems, Vol. VLSI-4, No. 2, pp. 286-291, June 1996.
    • (1996) IEEE Transactions on VLSI Systems , vol.VLSI-4 , Issue.2 , pp. 286-291
    • Neves, J.L.1    Friedman, E.G.2
  • 10
    • 0031165708 scopus 로고    scopus 로고
    • Buffered clock tree synthesis with non-zero clock skew scheduling for increased tolerance to process parameter variations
    • June/July
    • J. L. Neves and E. G. Friedman, "Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations, " Journal of VLSI Signal Processing, Volume 16, Numbers 2/3, pp. 149- 161, June/July 1997.
    • (1997) Journal of VLSI Signal Processing , vol.16 , Issue.2-3 , pp. 149-161
    • Neves, J.L.1    Friedman, E.G.2
  • 13
    • 0033280180 scopus 로고    scopus 로고
    • Synthesis of clock tree topologies to implement non-zero skew schedule
    • December
    • I. S. Kourtev and E. G. Friedman, "Synthesis of Clock Tree Topologies to Implement Non-Zero Skew Schedule, " IEE Proceedings-Circuits, Devices and Systems, Volume 146, No. 6, pp. 321-326, December 1999.
    • (1999) IEE Proceedings-circuits, Devices and Systems , vol.146 , Issue.6 , pp. 321-326
    • Kourtev, I.S.1    Friedman, E.G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.