Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 2-3, 1997, Pages 149-161

  Neves, José Luis ^{a,b,c,d,e,f,g}   Friedman, Eby G ^{a,h,i,j,k,l,m,n,o,p}  

^a University of Rochester   (United States)

^b FEDERAL UNIVERSITY OF MINAS GERAIS   (Brazil)

^c UNIVERSITY OF ROCHESTER   (United States)

^d UFMG   (Brazil)

^e IBM MICROELECTRONICS   (United States)

^f Ministério de Ciência Tecnologia e Inovação Salvador   (Brazil)

^g Tech Program Committee of ISCAS '97   (United States)

^h LAFAYETTE COLLEGE   (United States)

ⁱ UNIVERSITY OF CALIFORNIA   (United States)

^j PHILIPS RESEARCH LABORATORIES   (Germany)

^k RAYTHEON COMPANY   (United States)

^l Sign Proc Des and Test Department   (United States)

^m High Perf VLSI/IC Des Anal Lab   (United States)

ⁿ IEEE   (United States)

^o VLSI Syst Applic CAS Tech Comm   (United States)

^p VLSI ^*  (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; SYNCHRONIZATION; TREES (MATHEMATICS);

BENCHMARK CIRCUITS; BUFFERED CLOCK TREE SYNTHESIS; CLOCK SKEW SCHEDULE; SYNCHRONOUS DIGITAL CIRCUITS;

TIMING CIRCUITS;

EID: 0031165708     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (23)

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