Synthesis of clock tree topologies to implement nonzero clock skew schedule

IEE Proceedings: Circuits, Devices and Systems

Volumn 146, Issue 6, 1999, Pages 321-326

  Kourtev, I S ^a,b   Friedman, E G ^a,b  

^a UNIVERSITY OF ROCHESTER   (United States)

^b UNIVERSITY OF PITTSBURGH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MATHEMATICAL MODELS; PROBLEM SOLVING; SYNCHRONIZATION; TREES (MATHEMATICS);

CLOCK SKEW SCHEDULE;

TIMING CIRCUITS;

EID: 0033280180     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19990582     Document Type: Article

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