A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2005, Pages 65-72

  Kwon, Young Su ^a   Lajevardi, Payam ^a   Chandrakasan, Anantha P ^a   Honoré, Frank ^a   Troxel, Donald E ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3 D FPGA; Wire resource prediction

Indexed keywords

CHANNEL CAPACITY; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; PARAMETER ESTIMATION; RESOURCE ALLOCATION;

3-D FPGA; WIRE RESOURCE PREDICTION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 30944445428     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/1053355.1053371     Document Type: Conference Paper

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