Wiring requirement and three-dimensional integration of field-programmable gate arrays

2001 International Workshop on System-Level Interconnect Prediction (SLIP 2001)

Volumn , Issue , 2001, Pages 107-113

  Rahman, Arifur ^a   Das, Shamik ^b   Chandrakasan, Anantha ^b   Reif, Rafael ^b  

^a AGERE SYSTEMS   (United States)

^b Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

3 D integrated circuits; FPGA; System level modeling; Wire length

Indexed keywords

ELECTRIC WIRE; ELECTRIC WIRING; INTERCONNECTION NETWORKS; TABLE LOOKUP;

SYSTEM-LEVEL MODELING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035789319     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368640.368739     Document Type: Conference Paper

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