An asymmetric SRAM cell to lower gate leakage

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 534-539

  Azizi, Navid ^a   Najm, Farid N ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); HIGH FREQUENCY AMPLIFIERS; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; MOSFET DEVICES; PERMITTIVITY; TEMPERATURE DISTRIBUTION; THRESHOLD VOLTAGE;

GATE LEAKAGE; POWER DISSIPATION; THRESHOLD LEAKAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 2942640098     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2004.1283728     Document Type: Conference Paper

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