Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

IEEE Transactions on Nanotechnology

Volumn 2, Issue 4, 2003, Pages 210-216

  Choi, Woo Young ^a   Choi, Byung Yong ^a   Woo, Dong Soo ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

High speed; Low power; Low standby power (LSTP); Low operating power (LOP); MOSFET; Reverse order source drain formation with double offset spacer (RODOS)

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); OPTIMIZATION; POLYSILICON; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SWITCHING CIRCUITS;

GATE-DELAY; OFF-CURRENT; SWITCHING ENERGY;

MOSFET DEVICES;

EID: 3042725097     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2003.820805     Document Type: Conference Paper

References (16)

1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFET's and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
2. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "Sub-20 nm CMOS FinFET technologies," in IEEE Int. Electron Devices (IEDM) Tech. Dig., 2001, pp. 421-424.
3. W. Y. Choi, B. Y. Choi, D. S. Woo, Y. J. Choi, J. D. Lee, and B.-G. Park, "Side-gate design optimization of 50 nm MOSFET's with electrically induced source/drain," Jpn. J. Appl. Phys., vol. 41, pp. 2345-2347, Apr. 2002.
4. S. Takagi, "Strained-Si- and SiGe-on-insulator (strained-SOI and SGOI) MOSFET's for high performance/low power application," in Device Research Conf. Dig., 2002, pp. 37-40.
5. K. L. Lee, D. Boyd, J. Brancaccio, J. Bucchignano, J. Cai, K. Chan, H. Hanafi, P. Kozlowski, R. Miller, R. Roy, L. Shi, E. Sikorski, M. Surendra, S. Wind, Q. Yang, J. Yoon, C. Yu, Y. Zhang, and Y. Taur, "New polysilicon disposable sidewall process for sub-50 nm CMOS," in Proc. European Solid-State Device Res. Conf. (ESSDERC), 2001, pp. 159-162.
6. C.-L. Huang and N. D. Arora, "Measurements and modeling of MOSFET I-V characteristics with polysilicon depletion effect," IEEE Trans. Electron Devices, vol. 40, pp. 2330-2337, Dec. 1993.
7. C.-H. Choi, P. R. Chidambaram, R. Khamankar, C. F. Machala, Z. Yu, and R. W. Dutton, "Gate length dependent polysilicon depletion effects," IEEE Electron Device Lett., vol. 23, pp. 224-226, Apr. 2002.
8. S. Thompson, P. Packan, T. Ghani, M. Stettler, M. Alavi, I. Post, S. Tyagi, S. Ahmed, S. Yang, and M. Bohr, "Source/drain extension scaling for 0.1 μm and below channel length MOSFETs," in Symp. VLSI Technol. Dig. Tech. Papers, 1998, pp. 132-133.
9. S. K. H. Fung, M. Khare, D. Schepis, W. Lee, S. H. Ku, H. Park, J. Snare, B. Doris, A. Ajmera, K. P. Muller, P. Agnello, P. Gilbert, and J. Welser, "Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology," in IEDM Tech. Dig., 2001, pp. 629-632.
10. S. K. Sung, Y. J. Choi, J. D. Lee, and B.-G. Park, "Realization of ultrafine lines using sidewall structures and their application to nMOSFETs," J. Korean Phys. Soc., vol. 35, pp. 693-696, Dec. 1999.
11. W. Y. Choi, S. K. Sung, K. R. Kim, J. D. Lee, and B.-G. Park, "Nanoscale poly-Si line formation and its uniformity," in Proc. Asia-Pacific Workshop Fundamental and Application Advanced Semiconductor Devices, 2001 pp. 11-16.
12. T. Matsumoto, S. Maeda, K. Ota, Y. Hirano, K. Eikyu, H. Sayama, T. Iwan atsu, K. Yamamoto, T. Katoh, Y. Yamaguchi, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, and M. Inuishi, "70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications," in IEDM Tech. Dig., 2001, pp. 219-222.
13. M. T. Bohr, "Nanotechnology goals and challenges for electronic applications," IEEE Trans. Nanotechnology, vol. 1, pp. 56-62, Mar. 2002.
14. R. V. Langevelde, L. F. Tiemeijer, R. J. Havens, M. J. Knitel, R. F. M. Roes P. H. Woerlee, and D. B. M. Klaassen, "RF-distortion in deep-submicron CMOS technologies," in IEDM Tech. Dig.,2000, pp. 807-810.
15. P. H. Woerlee, M. J. Knitel, R. V. Langevelde, D. B. M. Klaasen, L. F. Tiemeijer, A. J. Scholten, and T. A. Z. Duijnhoven, "RF-CMOS performance trends," IEEE Trans. Electron Devices, vol. 48, pp. 1776-1782, Aug. 2001.
16. L. F. Tiemeijer, R. V. Langevelde, O. Gaillard, R. J. Havens, P. G. M. Baltus, P. H. Woerlee, and D. B. M. Klaassen, "RF distortion characterization of sub-micron CMOS," in Proc. European Solid-State Device Research Conf. (ESSDERC), 2000, pp. 464-467.