Analyzing SEU effects is SRAM-based FPGAsb

Proceedings - 9th IEEE International On-Line Testing Symposium, IOLTS 2003

Volumn , Issue , 2003, Pages 119-123

  Violante, M ^a   Ceschia, M ^b,c   Sonza Reorda, M ^a   Paccagnella, A ^b,c   Bernardi, P ^a   Rebaudengo, M ^a   Bortolato, D ^b   Bellato, M ^c   Zambolin, P ^b   Candelori, A ^c  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF PADOVA   (Italy)

^c SEZIONE DI PADOVA   (Italy)

Author keywords

CMOS technology; Costs; Face detection; Fault detection; Fault tolerant systems; Field programmable gate arrays; Prototypes; Silicon; Single event upset; Testing

Indexed keywords

CMOS INTEGRATED CIRCUITS; COSTS; FACE RECOGNITION; FAULT DETECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; RADIATION HARDENING; SILICON; STATIC RANDOM ACCESS STORAGE; TESTING;

CMOS TECHNOLOGY; COMMERCIAL OFF THE SHELVES; DEVICE CONFIGURATIONS; FAULT TOLERANT SYSTEMS; FPGA CONFIGURATION; PROTOTYPES; RADIATION TESTING; SINGLE EVENT UPSETS;

COMPUTER CONTROL SYSTEMS;

EID: 27944443776     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2003.1214377     Document Type: Conference Paper

References (10)

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