Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits

IEE Proceedings: Computers and Digital Techniques

Volumn 151, Issue 3, 2004, Pages 235-244

  Polian, I ^a   Pomeranz, I ^b   Reddy, S M ^c   Becker, B ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

^b PURDUE UNIVERSITY   (United States)

^c UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; FUNCTIONS; LOGIC CIRCUITS; SET THEORY; VECTORS;

COMBINATIONAL LOGIC; TEST GENERATION; TEST SETS; TESTER MEMORY;

ELECTRIC FAULT LOCATION;

EID: 2942733641     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20040141     Document Type: Article

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