Fault Collapsing via Functional Dominance

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 274-280

  Agrawal, Vishwani D ^a   Prasad, A V S S ^b   Atre, Madhusudan V ^b  

^a RUTGERS UNIVERSITY   (United States)

^b Agere Systems India Private Limited   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; LOGIC CIRCUITS; LOGIC GATES;

FAULT COLLAPSING;

INTEGRATED CIRCUIT TESTING;

EID: 0142246931     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

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