Short-channel modeling of bulk accumulation MOSFETs

IEEE Transactions on Electron Devices

Volumn 51, Issue 6, 2004, Pages 940-947

  Murali, Raghunath ^a   Austin, Blanca L ^b   Wang, Lihui ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b POLYTECHNIC UNIVERSITY OF PUERTO RICO   (Puerto Rico)

Author keywords

Accumulation; Buried channel; Inversion; MOSFET; Short channel; Threshold voltage

Indexed keywords

ELECTRIC CURRENTS; MATHEMATICAL MODELS; OPTIMIZATION; THRESHOLD VOLTAGE;

ACCUMULATION; BURIER CHANNEL; INVERSION; SHORT CHANNEL MODELING;

MOSFET DEVICES;

EID: 2942672647     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.828276     Document Type: Article

References (21)

1. T. Enda and N. Shigyo, "Alleviation of subthreshold swing and short-channel effect in buried-channel MOSFETs: the counter-doped surface-channel MOSFET structure," Elect. Comm., vol. 79, no. 11, pp. 43-49, Nov. 1996.
2. A. W. Vinal, "Fermi threshold field effect transistor," U.S. Patent Number 4 990 974, Feb. 5, 1991.
3. T. Yoshitomi, M. Saito, H. Oguma, Y. Akasaka, M. Ono, H. Nii, Y. Ushiku, H. Iwai, and H. Hara, "Ultrashallow buried-channel p-MOSFET with extremely high transconductance," in Symp. VLSI Tech. Dig., 1993, pp. 99-100.
4. th and high SCE immunity of buried-channel PMOS-FETs in 4-Gbit DRAMs and beyond," in Symp. VLSI Tech. Dig., 1998, pp. 88-89.
5. S. Inaba, R. Katsumata, H. Akatsu, R. Rengarajan, P. Ronsheim, G. S. Murthy, K. Sunouchi, and G. B. Bronner, "Threshold voltage roll-up/roll-off characteristic control in sub-0.2-um single workfunction gate CMOS for high-performance DRAM applications," IEEE Trans. Electron Devices, vol. 49, pp. 308-313, Feb. 2002.
6. C. Bulucea and D. Kerr, "Threshold voltage control in buried-channel MOSFETs," Solid State Electron., vol. 41, pp. 1345-1354, 1997.
7. M. J. Van der Tol and S. G. Chamberlain, "Potential and electron distribution model for the buried-channel MOSFET," IEEE Trans. Electron Devices, vol. 36, pp. 670-689, Apr. 1989.
8. Y. Yin and J. A. Cooper Jr., "Simple equations for the electrostatic potential in buried-channel MOS devices," IEEE Trans. Electron Devices, vol. 39, pp. 1770-1772, July 1992.
9. Y.-T. Lee, D.-S. Woo, J. D. Lee, and B.-G. Park, "Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D poisson equation," IEEE Trans. Electron Devices, vol. 47, pp. 2326-2333, Dec. 2000.
10. T. Skotnicki, G. Merckel, and T. Pedron, "Analytical study of punchthrough buried-channel P-MOSFETs," IEEE Trans. Electron Devices, vol. 36, pp. 690-705, Apr. 1989.
11. M. J. Van der Tol and S. G. Chamberlain, "Drain-induced barrier lowering in buried-channel MOSFETs," IEEE Trans. Electron Devices, vol. 40, pp. 741-749, Apr. 1993.
12. K. N. Ratnakumar and J. D, Meindl, "Short-channel MOST threshold voltage model," IEEE J. Solid-State Circuits, vol. SC-17, pp. 937-947, Oct. 1982.
13. ISE DESSIS: Release 8.0, Integrated Systems Engineering, 2002.
14. Q. Chen, B. Agrawal, and J. D. Meindl, "A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 1086-1090, June 2002.
15. R. M. Swanson and J. D. Meindl, "Ion-implanted complementary MOS transistors in low-voltage circuits," IEEE J. Solid-State Circuits, vol. SC-7, pp. 146-153, Apr. 1972.
16. B. L. Austin, "Performance analysis and scaling opportunities of bulk cmos inversion and accumulation devices," Ph.D. dissertation, Georgia Tech, Atlanta, GA, May 2001.
17. A. Asenov and S. Saini, "Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-um MOSFETs with epitaxial and δ-doped channels," IEEE Trans. Electron Devices, vol. 46, pp. 1718-1724, Aug. 1999.
18. S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
19. R. Chau, R. Arghavani, D. Barlage, G. Dewey, B. Doyle, M. Doczy, J. Kavalieros, D. Lionberger, A. Murthy, B. Roberds, and R. Schenker, "30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays," in IEDM Tech. Dig., 2000, pp. 45-48.
20. K. A. Bowman, L. Wang, X. Tang, and J. D. Meindl, "A circuit level perspective of the optimum gate oxide thickness," IEEE Trans. Electron Devices, vol. 48, pp. 1800-1810, Aug. 2001.
21. Semiconductor Industry Association, The International Technology Roadmap for Semiconductors, 2002.