Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D poisson equation

IEEE Transactions on Electron Devices

Volumn 47, Issue 12, 2000, Pages 2326-2333

  Lee, Yeong Taek ^a   Woo, Dong Soo ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

Buried channel; Counter doping; Pmosfet; Quasi 2 D; Threshold voltage reduction

Indexed keywords

EID: 2942695991     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.887015     Document Type: Article

References (17)

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