A 2 Gb/s balanced AES crypto-chip implementation

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 39-44

  Gurkaynak F K ^a   Burg, A ^a   Felber, N ^a   Fichtner, W ^a   Gasser, D ^a   Hug, F ^a   Kaeslin, H ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

AES; ASIC implementation; Rijndael

Indexed keywords

ADVANCED ENRCYPTION STANDARD (AES); DECRYPTION; INTERCONNECTION WIRES; REGISTER TRANSFER LEVEL OPTIMIZATION;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COUNTING CIRCUITS; CRYPTOGRAPHY; FEEDBACK; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 2942656956     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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