2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2523, Issue , 2003, Pages 144-158

  Lutz, A K ^a   Treichler, J ^a   Gurkaynak F K ^a   Kaeslin, H ^a   Basler, G ^a   Erni, A ^a   Reichmuth, S ^a   Rommens, P ^a   Oetiker, S ^a   Fichtner, W ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; HARDWARE;

CIPHER ALGORITHMS; CIRCUIT COMPLEXITY; CMOS TECHNOLOGY; COMPARATIVE ANALYSIS; DEDICATED HARDWARE; FABRICATION PROCESS; HARDWARE REALIZATION; VLSI IMPLEMENTATION;

CRYPTOGRAPHY;

EID: 21544470484     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-36400-5_12     Document Type: Article

References (12)

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3. Nechvatal, J., Barker, E., Bassham, L., Burr, W., Dworkin, M., Foti, J., Roback, E.: Report on the Development of the Advanced Encryption Standard (AES). NIST, Computer Security Division, Information Technology Laboratory, October 2000.
4. Weeks, B., Bean, M., Rozylowicz, T., Ficke, C.: Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms. National Security Agency (NSA).
5. Kaeslin, H.: From Algorithms to Architectures. Lecture Notes in VLSI Design, Microelectronics Design Center, ETH Zürich.
6. Kuo, H., Verbauwhede, I.: Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the Rijndael Algorithm. Proceedings of the Third International Workshop of Cryptographic Hardware and Embedded Systems CHES 2001, Paris, May 2001.
7. Elbirt, A., Yip, W., Chetwynd, B., Paar, C.: An FPGA-Based Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. IEEE Transactions on VLSI, August 2001, vol. 9, no. 4, 545-557.
8. Ichikawa, T., Kasuya, T., Matsui, M.: Hardware Evaluation of the AES Finalists. Proceedings of the Third Advanced Encryption Standard Candidate Conference, New York, April 2000, 279-285.
9. Gaj, K., Chodowiec, P.: Comparison of the hardware performance of the AES candidates using reconfigurable hardware. Proceedings of the Third Advanced Encryption Standard Candidate Conference, New York, April 2000, 40-54.
10. Weaver, N., Wawrzynek, J.: A Comparison of the AES Candidates Amenability to FPGA Implementation. Proceedings of the Third Advanced Encryption Standard Candidate Conference, New York, April 2000, 28-39.
11. Gaj, K., Chodowiec, P.: Hardware performance of the AES finalists - survey and analysis of results. Technical Report, George Mason University, September 2000.
12. Dworkin, M.: Recommendation for Block Cipher Modes of Operation - Methods and Techniques. NIST Special Publication 800-38A, 2001.