A 2.3Gb/s fully integrated and synthesizable AES rijndael core

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 193-196

  Kim, Nam Sung ^a   Mudge, Trevor ^a   Brown, Richard ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; ELECTRONIC COMMERCE; INTEGRATED CIRCUIT MANUFACTURE; INTELLECTUAL PROPERTY; INTERNET; NETWORK PROTOCOLS; SECURITY OF DATA;

ADVANCED ENCRYPTION STANDARD; CIPHER CORE; DECIPHER SYSTEMS; ENCIPHER SYSTEMS; VIRTUAL PRIVATE NETWORKS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242527299     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. J. Daemen and V. Rijmen, "The Rijndael Block Cipher", AES Proposal, http://csrc.nist.gov/encryption/aes, 2001.
4. H. Kuo et al., "A 2.29 Gbits/sec, 56mW Non-Pipelined Rijndael AES Encryption IC in a 1.8V, 0.18um CMOS Technology", Custom Integrated Circuits Conf., 2002.
5. C. Lu et al., "Integrated design of AES encrypter and decrypter", Proc. Intl. Conf. on Application-Specific Systems, Architectures and Processors, 2002.
6. T. Lin et al., "A high-throughput low-cost AES cipher chip", Proc. Asia-Pacific Conf. on ASIC, 2002.
7. S. Morioka et al., "A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture", Intl. Conf on Computer Design: VLSI in Computers and Processors, 2002.