Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon thin film transistors

Journal of Applied Physics

Volumn 95, Issue 10, 2004, Pages 5788-5794

  Chen, Tien Fu ^a   Yeh, Ching Fa ^a   Lou, Jen Chung ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ELECTRON TRAPS; EXCIMER LASERS; GRAIN BOUNDARIES; HOT CARRIERS; LEAKAGE CURRENTS; POLYCRYSTALLINE MATERIALS; SEMICONDUCTOR JUNCTIONS; THIN FILM TRANSISTORS; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

DRAIN JUNCTIONS; PLASMA TREATMENT; STRESS TIME; SYSTEM ON A PANEL (SOP);

SILICON;

EID: 2942609448     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1699504     Document Type: Article

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