Evaluation of statistical outlier rejection methods for IDDQ limit setting

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 755-760

  Sabade, S ^a   Walker, H ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT TESTING; STATISTICS; TESTING;

CHAUVENET'S CRITERION; LIMIT SETTING; OUTLIER REJECTION; PASS/FAIL LIMITS; QUIESCENT CURRENTS; STATIC THRESHOLDS; SUB-THRESHOLD LEAKAGE CURRENTS; TESTING METHOD;

DESIGN;

EID: 2942526614     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.995024     Document Type: Conference Paper

References (31)

1. DDQ Testing: A Review," Journal of Electronic Testing: Theory and Applications, 1992.
2. DDQ Testing in CMOS Digital ASICs," Journal of Electronic Testing: Theory and Applications, (JETTA), 1992.
3. DDQ Benefits," Proc. of IEEE VLSI Test Symposium, 1991.
4. DDQ," Journal of Electronic Testing: Theory and Applications, 1992.
5. K. Wallquist, "On the Effect of ISSQ Testing in Reducing Early Failure Rate," Intl. Test Conf., 1995.
6. DDQ Testing for CMOS VLSI," Proceeding of the IEEE, April 2000.
7. M. Jacomino et al., "Fault Detection in CMOS Circuits by Consumption Measurement," IEEE Trans. on Instrumentation and Measurement vol. 38, No. 3, June 1989, pp.773-778.
8. DDQ Testing, 1998.
9. Ali Keshavarzi et al., "Intrinsic Leakage in Deep Submicron CMOS ICs - Measurement-Based Test Solutions," IEEE Trans. on VLSI Systems, Dec. 2000.
10. DDQ Testing: Issues and Solutions," Proc. of European Design & Test Conf., 1997.
11. DDQ Testing for Large ICs," VLSI Design vol. 1, no. 4, 1994.
12. DDQ Testing of Bridging Faults," Institute of Electronics, Information and Communication Engineers (IEICE) Trans. on Information and Systems, Vol. E81-D, No.7, July 1998.
13. DDQ Testing: A Case Study," IEEE Design & Test of Computers, Summer 1995.
14. Semiconductor Industries Association, International Technology Roadmap for Semiconductors, 1999.
15. DDQ Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics," Journal of Electronic Testing: Theory and Applications", 1992.
16. Charles Hawkins and Jerry Soden, "Deep Sub-micron IC Testing: Is There A Future?," IEEE Design & Test of Computers, Oct-Dec. 1999.
17. Brian Stine et al., "Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices," IEEE Trans. on Semi. Manufacturing Vol. 10, No. 1, Feb. 1997
18. Anne Gattiker and Wojciech Maly, "Current Signatures," IEEE VLSI Test Symposium, 1996.
19. DDQ Testing, Oct. 1996.
20. C. Thibeault, "A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures," IEEE VLSI Test Symposium, 1997.
21. C. Thibeault, "An Histogram based procedure for current testing of active defects," Intl. Test Conference, 1999.
22. DDQ Testing," Intl. Test Conference, 2000.
23. DDQ Workshop, 1998.
24. DDQ Testing," Intl. Test Conference, 1999.
25. DDQ Data," Intl. Test Conference, 2000, pp.189-198.
26. DDQ Testing, 1997.
27. Adit Singh et al., "Binning for IC Quality: Experimental Studies on the SEMATECH Data", Intl. Symp. on Defect and Fault Tolerance in VLSI Systems, 1998.
28. Stuart Meyer, "Data Analysis for Scientists and Engineers," John Wiley & Sons, 1975.
29. st Ed., University Science Books, CA, 1982.
30. Ronald Richmond, "Successful Implementation of Structured Testing," Intl. Test Conference, 2000 Atlantic City, pp. 344-348
31. Phil Nigh et al., "An experimental study comparing the relative effectiveness of functional, scan, IDDQ and delay fault testing," IEEE VLSI Test Symposium, 1997.