Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 276-281

  Loghi, Mirko ^a   Letis, Martin ^a   Benini, Luca ^b   Poncino, Massimo ^c  

^a UNIVERSITY OF VERONA   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c POLITECNICO DI TORINO   (Italy)

Author keywords

Cache Coherence; Low Power; Multiprocessor; System on Chip

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; LOGIC PROGRAMMING; MICROPROCESSOR CHIPS;

CACHE COHERENCE; LOW POWER; SINGLE-CHIP MULTI-PROCESSORS; SYSTEM-ON-CHIP;

ENERGY EFFICIENCY;

EID: 29244472212     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1057661.1057728     Document Type: Conference Paper

References (34)

1. "Broadening the Reach of the Intel Itanium 2 Processor Family,"Technical White Paper, www.intel.com/ebusiness/pdf/prod/itanium/ wp_reach.pdf
2. M. Tremblay, J. Chen, S. Chaudry, A. Conigliaro, S.-S. Tse. "The MAJC Architecture: A Synthesis of Parallelism and Scalability,", IEEE Micro, Vol. 20, No. 6, Nov.-Dec. 2000, pp 12-25.
3. J.M. Tendler, J.S. Dodson, J.S. Fields Jr., H. Le, B. Sin-Haroy. "POWER4 System Microarchitecture," IBM Journal of Research and Development, Vol. 46, No. 1, January 2002.
4. P. Cumming "The TI OMAP Platform Approach to SoC,"in Winning the SOC Revolution, Kluwer Academic Publishers, 2003.
5. S. Richardson, "MPOC:A Chip Multiprocessor for Embedded Systems,",HP Technical Report, HPL-2002-186, July 2002.
6. B. Ackland et al., 'A Single Chip, 1.6 Billion, 16-b MAC/s Multiprocessor DSP,"IEEE Journal of Solid State Circuits, Vol. 35, No. 3, March 2000.
7. Philips Semiconductor, "PhilipsNexperia Platform", www.semiconductors.philips.com/products/nexperia/home S. Dutta, R. Jensen, A. Rieckmann
8. M. Grammatikakis, M. Coppola, F. Sensini, "Software for Multiprocessor Networks-on-Chip,"Network on Chip, Kluwer Academic Publishers, pp. 281-303, 2003.
9. E. Aarts, R. Roovers, "ICDesign Challenges for Ambient Intelligence," Design, Automation and Test in Europe, pp. 3-7, 2003.
10. L. Benini, M. Poncino, "Ambient Intelligence: A Computational Platform Perspective" in: Ambient Intelligence: Impact on Embedded System Design, T. Basten, M. Geilen, H. de Groot eds. Kluwer Academic Publishers, 2003.
11. A. Macii, L. Benini, M. Poncino, Memory Design Techniques for Low-Energy Embedded Systems, Kluwer Academic Publishers, 2002.
12. C. Lin, L. Snyder, "A Comparison of Programming Models for Shared Memory Multiprocessors."International Conference on Parallel Processing, pp. 163-170, 1990.
13. T.J. LeBlanc, E.P. Markatos, "Sharedmemory vs. message passing in shared-memory multiprocessors,"Symposium on Parallel and Distributed Processing, pp. 254-263, Dec. 1992.
14. A.C. Klaiber, H.M. Levy, "A Comparison of Message Passing and Shared Memory Architectures for Data Parallel Programs,"ISCA'94: International Symposium on Computer Architecture, pp. 94-105, 1994.
15. S. Chandra, J. R. Larus, A. Rogers, "Whereis Time Spent in Message-Passing and Shared-Memory Programs?" ASPLOS'94: International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 61-73, 1994.
16. S. Karlsson and M. Brorsson. "A comparative characterization of communication patterns in applications using MPI and shared memory on an IBM SPI,"International.Worlishop on Communication, Architecture, and Applications for Network-Based Parallel Computing, pp. 189-201, 1998.
17. H. Shan, J.P. Singh, L. Oliker, R. Biswas, "Message passing vs. shared address space on a cluster of SMPs,"International Parallel and Distributed Processing Symposium, April 2001.
18. D.E. Culler, A. Gupta. J.P. Singh, Parallel Computer Architecture: A Hardware/Software Approach Morgan Kaufmann Publishers, 1997.
19. M. Ekman, F. Dahlgren, P. Stenström "Evaluation of Snoop-Energy Reduction Techniques for Chip-Multiprocessors," Workshop on Duplicating, Deconstructing and Debunking - in conjunction with ISCA'02: International Symposium on Computer Architecture, May 2002. ISCA'02, May 2002.
20. M. Ekman, F. Dahgren, P. Stenström, "TLB and Snoop Energy-Reduction Using Virtual Caches in Low-Power Chip-Multiprocessors" ISLPED'02: International Symposium on Low Power Electronics and Design, August 2002, pp. 243-246.
21. M. Loghi, M. Poncino, "ExploringEnergy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions"DATE'05: Design, Automation and Test in Europe, to appear.
22. P. Stenström, "A Survey of Cache Coherence Schemes for Multiprocessors," IEEE Computer, Vol. 23, No. 6, June 1990, pp. 12-24.
23. M. Tomasevic, V. M. Milutinovic, "Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors,"IEEE Micro, Vol. 14, No. 5-6, pp. 52-59, October/December 1994.
24. I. Tartalja, V. M. Milutinovic, "Classifying Software-Based Cache Coherence Solutions,"IEEE Software, Vol. 14, No. 3, pp. 90-101, March 1997.
25. A. Moshovos, B. Falsafi, A. Choudhary, "JETTY Filtering Snoops for Reduced Energy Consumption in SMP Servers", HPCA'01 January 2001, pp. 85-97.
26. C. Saldanha and M. Lipasti, "Paver Efficient Cache Coherence", High Performance Memory Systems, Springer-Verlag, 2003, pp. 63-78.
27. M. Loghi, F Angiolini, D. Bertozzi, L. Benini, R. Zafalon, "Analyzing On-Chip Communication in a MPSoC Environment".DATE'04: Design, Automation and Test in Europe, February 2004, pp. 752-757.
28. Software ARM, www.g141.com/projects/swarm.
29. ARM Ltd., www.arm.com/products/solutions/AMBAHomePage.html
30. RTEMS home page, www.rtems.com.
31. L. Benini et al. "A power modeling and estimation framework for VLIW-based embedded systems,"PATMOS'01, October 2001, pp. 26-28.
32. M. Chinosi, R. Zafalon, C. Guardiani, 'Automatic Characterization and Modeling of Power Consumption in Static RAMs,"ISLPED'98, Aug. 1998, pp. 112-114.
33. A. Bona, V. Zaccaria, R. Zafalon, "System-Level Power Modeling and Simulation of High-End Industrial Network-on-chip",DATE'04,pp. 318-323.
34. J. P. Singh, W.-D. Weber, A. Gupta, "SPLASH:Stanford Parallel Applications for Shared-Memory", Computer Architecture News, Vol. 20, No. 1, pages 5-44, March 1992.