Exploring area/delay tradeoffs in an AES FPGA implementation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3203, Issue , 2004, Pages 575-585

  Zambreno, Joseph ^a   Nguyen, David ^a   Choudhary, Alok ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCE; CRYPTOGRAPHY; DATA PRIVACY; EFFICIENCY; INTEGRATED CIRCUITS; PARETO PRINCIPLE; STANDARDS;

ADVANCED ENCRYPTION STANDARD; AREA EFFICIENCY; BUILDING BLOCKES; COST EFFICIENCY; DESIGN DECISIONS; FPGA IMPLEMENTATIONS; PARETO-OPTIMAL; SOFTWARE IMPLEMENTATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 29244455761     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_59     Document Type: Article

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