A 10-bit, 3.3-V, 60Msample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Nejati, Babak ^a   Shoaei, Omid ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG-TO-DIGITAL CONVERTERS (ADC); CMOS TECHNOLOGY; HISTOGRAMS; SAMPLING RATES;

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FAST FOURIER TRANSFORMS; HARMONIC GENERATION; MODULATION; OPERATIONAL AMPLIFIERS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; SAMPLING; SIGNAL TO NOISE RATIO;

ANALOG TO DIGITAL CONVERSION;

EID: 4344602903     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. I. Mehr and L. Singer, "A 55-mW, 10-Bit, 40-Msample/s Nyquist-Rate CMOS ADC", IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, Mar. 2000, pp. 318-25.
2. I. E. Opris, L. D. Lewicki, and B. C. Wong, "A Single-Ended 12-bit 20 Msample/s Self-Calibrating Pipeline A/D Converter", IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, Dec. 1998. pp. 1898-903
3. O. E. Erdogan, P. J. Hurst, S. H. Lewis, "A 12-b Digital-Background calibrated Algorithmic ADC with -90-dB THD", IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, Dec. 1999, pp. 1812-20.
4. M. Choe, B. Song, and K. Bacrania, "A 13-b 40-Msample/s CMOS Pipelined Folding ADC with Background Offset Trimming", IEEE Journal of Solid-State Circuits, Vol. 35, No. 12, Dec. 2000, pp. 1781-90.
5. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, Vol. 34, May 1999, pp. 599-606.
6. A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, "A 15-b, 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, Vol. 28, Dec. 1993, pp. 1207-14.
7. S.-H. Lee and B.-S. Song, "Digital-domain calibration of multistep analog-to-digital converters," IEEE J. Solid-State Circuits, Vol. 27, Dec. 1992, pp. 1679-88,.
8. W. Eberle, et al., "A Digital 72Mb/s 64-QAM OFDM Transceiver for 5GHz Wireless LAN in 0.18-μm CMOS," IEEE International Solid-State Circuits Conference, pp. 336-7, 2001
9. B. Nejati, O. Shoaei, "A 10-bit, 2.5-V, 40MSample/S, Pipelined Analog-to-Digital Converter in 0.6-μm CMOS," IEEE International Symposium on Circuits and Systems 2001
10. B. Nejati, O. Shoaei, "Combined radix<2 and 1.5 bit/stage pipelined analogue-to-digital converter," IEE Electronics Letters, Vol. 39, Jan. 2003, pp. 2-4.