-
1
-
-
0024122165
-
"Queuing in high-performance packet-switching"
-
Dec
-
M. Karol and M. Hluchyj, "Queuing in high-performance packet-switching," IEEE J. Sel. Areas Commun., vol. 6, no. 12, pp. 1587-1597, Dec. 1988.
-
(1988)
IEEE J. Sel. Areas Commun.
, vol.6
, Issue.12
, pp. 1587-1597
-
-
Karol, M.1
Hluchyj, M.2
-
2
-
-
0027694638
-
"High speed switch scheduling for local area networks"
-
Nov
-
T. Anderson, S. Owicki, J. Saxe, and C. Thacker, "High speed switch scheduling for local area networks," ACM Trans. Comput. Syst., vol. 11, no. 4, pp. 319-352, Nov. 1993.
-
(1993)
ACM Trans. Comput. Syst.
, vol.11
, Issue.4
, pp. 319-352
-
-
Anderson, T.1
Owicki, S.2
Saxe, J.3
Thacker, C.4
-
3
-
-
0033349686
-
"Achieving 100% throughput in an input-queued switch"
-
Aug
-
N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, "Achieving 100% throughput in an input-queued switch," IEEE Trans. Commun., vol. 47, no. 8, pp. 1260-1267, Aug. 1999.
-
(1999)
IEEE Trans. Commun.
, vol.47
, Issue.8
, pp. 1260-1267
-
-
McKeown, N.1
Mekkittikul, A.2
Anantharam, V.3
Walrand, J.4
-
4
-
-
0031649903
-
"A practical scheduling algorithm to achieve 100% throughput in input-queued switches"
-
Mar
-
A. Mekkittikul and N. McKeown, "A practical scheduling algorithm to achieve 100% throughput in input-queued switches," in Proc. INFOCOM, vol. 2, Mar. 1998, pp. 792-799.
-
(1998)
Proc. INFOCOM
, vol.2
, pp. 792-799
-
-
Mekkittikul, A.1
McKeown, N.2
-
5
-
-
0032655137
-
"The iSLIP scheduling algorithm for input-queue switches"
-
Apr
-
N. McKeown, "The iSLIP scheduling algorithm for input-queue switches," IEEE/ACM Trans. Netw., vol. 7, no. 2, pp. 188-200, Apr. 1999.
-
(1999)
IEEE/ACM Trans. Netw.
, vol.7
, Issue.2
, pp. 188-200
-
-
McKeown, N.1
-
6
-
-
0032673103
-
"On the speedup required for work-conserving crossbar switches"
-
Jun
-
P. P. Krishna, N. S. Patel, A. Charny, and R. Simcoe, "On the speedup required for work-conserving crossbar switches," IEEE J. Sel. Areas Commun., vol. 27, no. 6, pp. 1052-1066, Jun. 1999.
-
(1999)
IEEE J. Sel. Areas Commun.
, vol.27
, Issue.6
, pp. 1052-1066
-
-
Krishna, P.P.1
Patel, N.S.2
Charny, A.3
Simcoe, R.4
-
7
-
-
0032663268
-
"Analysis of nonblocking ATM switches with multiple input queues"
-
Feb
-
G. Nong, J. K. Muppala, and M. Hamdi, "Analysis of nonblocking ATM switches with multiple input queues," IEEE/ACM Trans. Netw., vol. 7. no. 1, pp. 60-74, Feb. 1999.
-
(1999)
IEEE/ACM Trans. Netw.
, vol.7
, Issue.1
, pp. 60-74
-
-
Nong, G.1
Muppala, J.K.2
Hamdi, M.3
-
8
-
-
0035416658
-
"Performance evaluation of multiple input-queued ATM switches with PIM scheduling under bursty traffic"
-
Aug
-
G. Nong, M. Hamdi, and J. K. Muppala, "Performance evaluation of multiple input-queued ATM switches with PIM scheduling under bursty traffic," IEEE Trans. Commun., vol. 49. no. 8, pp. 1329-1333, Aug. 2001.
-
(2001)
IEEE Trans. Commun.
, vol.49
, Issue.8
, pp. 1329-1333
-
-
Nong, G.1
Hamdi, M.2
Muppala, J.K.3
-
9
-
-
0030871480
-
"Tiny Tera: A packet switch core"
-
Jan.-Feb
-
N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick, and M. Horowitz, "Tiny Tera: A packet switch core," IEEE Micro, vol. 17, no. 1, pp. 26-33, Jan.-Feb. 1997.
-
(1997)
IEEE Micro.
, vol.17
, Issue.1
, pp. 26-33
-
-
McKeown, N.1
Izzard, M.2
Mekkittikul, A.3
Ellersick, W.4
Horowitz, M.5
-
10
-
-
28844506647
-
GS40 0.11-μm CMOS, Standard Cell/Gate Array
-
Texas Instruments. (Jan.) ver.1.0. [Online]. Available
-
Texas Instruments. (2001, Jan.) GS40 0.11-μm CMOS, Standard Cell/Gate Array, ver.1.0. [Online]. Available: http://www.ti.com/
-
(2001)
-
-
-
11
-
-
0023435613
-
"Integrated packet network using bus matrix"
-
Oct
-
S. Nojima, E. Tsutsui, H. Fukuda, and M. Hashimmoto, "Integrated packet network using bus matrix," IEEE J. Sel. Areas Commun., vol. SAC-5, no. 8, pp. 1284-1291, Oct. 1987.
-
(1987)
IEEE J. Sel. Areas Commun.
, vol.SAC-5
, Issue.8
, pp. 1284-1291
-
-
Nojima, S.1
Tsutsui, E.2
Fukuda, H.3
Hashimmoto, M.4
-
12
-
-
85176425027
-
"16 × 16 limited intermediate buffer switch module for ATM networks"
-
Dec
-
A. K. Gupta, L. O. Barbosa, and N. D. Georganas, "16 × 16 limited intermediate buffer switch module for ATM networks," in Proc. GLOBECOM, Dec. 1991, pp. 939-943.
-
(1991)
Proc. GLOBECOM
, pp. 939-943
-
-
Gupta, A.K.1
Barbosa, L.O.2
Georganas, N.D.3
-
13
-
-
28844491643
-
"Limited intermediate buffer switch modules and their interconnection networks for B-ISDN"
-
Jun
-
A. K. Gupta, L. O. Barbosa, and N. D. Georganas, "Limited intermediate buffer switch modules and their interconnection networks for B-ISDN," in Proc. Int. Conf. Commun., Jun. 1992, pp. 1646-1650.
-
(1992)
Proc. Int. Conf. Commun.
, pp. 1646-1650
-
-
Gupta, A.K.1
Barbosa, L.O.2
Georganas, N.D.3
-
14
-
-
0033280278
-
"A 10-Gb/s (1.25 Gb/s × 8) 4 × 0.25 - μm CMOS/SIMOX ATM switch based on scalable distributed arbitration"
-
Dec
-
E. Oki, N. Yamanaka, Y. Ohtomo, K. Okazaki, and R. Kawano, "A 10-Gb/s (1.25 Gb/s × 8) 4 × 0.25 - μm CMOS/SIMOX ATM switch based on scalable distributed arbitration," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1921-1934, Dec. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.12
, pp. 1921-1934
-
-
Oki, E.1
Yamanaka, N.2
Ohtomo, Y.3
Okazaki, K.4
Kawano, R.5
-
15
-
-
0027562052
-
"A high-speed ATM switch with input and cross-point buffers"
-
Mar
-
Y. Doi and N. Yamanaka, "A high-speed ATM switch with input and cross-point buffers," IEICE Trans. Commun., vol. E76, no. 3, pp. 310-314, Mar. 1993.
-
(1993)
IEICE Trans. Commun.
, vol.E76
, Issue.3
, pp. 310-314
-
-
Doi, Y.1
Yamanaka, N.2
-
16
-
-
0025211581
-
"Fast packet switch architectures for broadband integrated services digital networks"
-
Jan
-
F. A. Tobagi, "Fast packet switch architectures for broadband integrated services digital networks," Proc. IEEE, vol. 78, no. 1, pp. 133-167, Jan. 1990.
-
(1990)
Proc. IEEE
, vol.78
, Issue.1
, pp. 133-167
-
-
Tobagi, F.A.1
-
17
-
-
0024733794
-
"A survey of modern high-performance switching techniques"
-
Sep
-
H. Ahmadi and W. E. Denzel, "A survey of modern high-performance switching techniques," IEEE J. Sel. Areas Commun., vol. 7, no. 7, pp. 1091-1103, Sep. 1989.
-
(1989)
IEEE J. Sel. Areas Commun.
, vol.7
, Issue.7
, pp. 1091-1103
-
-
Ahmadi, H.1
Denzel, W.E.2
-
18
-
-
0029403293
-
"Survey of ATM switch architectures"
-
Nov
-
R. Y. Awdeh and H. T. Mouftah, "Survey of ATM switch architectures," Comput. Netw. ISDN Syst., vol. 27, pp. 1567-1613, Nov. 1995.
-
(1995)
Comput. Netw. ISDN Syst.
, vol.27
, pp. 1567-1613
-
-
Awdeh, R.Y.1
Mouftah, H.T.2
-
19
-
-
0031648315
-
"Implementing distributed packet fair queuing in a scalable switch architecture"
-
D. C. Stephen and H. Zhang, "Implementing distributed packet fair queuing in a scalable switch architecture," in Proc. INFOCOM, vol. 1, 1998, pp. 282-290.
-
(1998)
Proc. INFOCOM
, vol.1
, pp. 282-290
-
-
Stephen, D.C.1
Zhang, H.2
-
20
-
-
0034462558
-
"A distributed scheduling architecture for scalable packet switches"
-
Dec
-
F. M.. Chiussi and A. Francini, "A distributed scheduling architecture for scalable packet switches," IEEE J. Sel. Areas Commun., vol. 18, no. 12, pp. 2665-2683, Dec. 2000.
-
(2000)
IEEE J. Sel. Areas Commun.
, vol.18
, Issue.12
, pp. 2665-2683
-
-
Chiussi, F.M.1
Francini, A.2
-
21
-
-
0035785965
-
"CIXB-1: Combined input-one-cell-crosspoint buffered switch"
-
May
-
R. Rojas-Cessa, E. Oki, Z. Jing, and H. J. Chao, "CIXB-1: Combined input-one-cell-crosspoint buffered switch," in Proc. IEEE Workshop High Perform. Switching Routing, May 2001, pp. 324-329.
-
(2001)
Proc. IEEE Workshop High Perform. Switching Routing
, pp. 324-329
-
-
Rojas-Cessa, R.1
Oki, E.2
Jing, Z.3
Chao, H.J.4
-
22
-
-
0029756982
-
"Backpressure in shared-memory based atm switches under multiplexed bursty sources"
-
Mar
-
F. M. Chiussi, Y. Xia, and V. P. Kumar, "Backpressure in shared-memory based atm switches under multiplexed bursty sources," in IEEE INFOCOM, Mar. 1996, pp. 830-843.
-
(1996)
IEEE INFOCOM
, pp. 830-843
-
-
Chiussi, F.M.1
Xia, Y.2
Kumar, V.P.3
-
23
-
-
0030638095
-
"An efficient scheduling algorithm for input-queuing ATM switches"
-
B. Li, M. Hamdi, and X-R. Cao, "An efficient scheduling algorithm for input-queuing ATM switches," in Proc. IEEE Broadband Switching Syst., 1997, pp. 148-154.
-
(1997)
Proc. IEEE Broadband Switching Syst.
, pp. 148-154
-
-
Li, B.1
Hamdi, M.2
Cao, X.-R.3
-
24
-
-
0035785791
-
"Load balanced Birkhoff-von Neumann switches"
-
May
-
C-S. Chang, D-S. Lee, and Y-S. Jou, "Load balanced Birkhoff-von Neumann switches," in Proc. IEEE Workshop High Perform. Switching Routing, May 2001, pp. 276-280.
-
(2001)
Proc. IEEE Workshop High Perform. Switching Routing
, pp. 276-280
-
-
Chang, C.-S.1
Lee, D.-S.2
Jou, Y.-S.3
-
25
-
-
84889295426
-
Weighted arbitration algorithms with priorities for input-queued switches with 100% throughput
-
presented at Proc. Broadband Switching Symp.. [Online]. Available
-
R. Schoenen, G. Post, and G. Sander. Weighted arbitration algorithms with priorities for input-queued switches with 100% throughput. presented at Proc. Broadband Switching Symp.. [Online]. Available: http://www.schoenen-service.de/assets/papers/Schoenen99bssw.pdf
-
-
-
Schoenen, R.1
Post, G.2
Sander, G.3
-
26
-
-
0842289194
-
"Output queued switch emulation by a one-cell-internally buffered crossbar switch"
-
Dec
-
L. Mhamdi and M. Hamdi, "Output queued switch emulation by a one-cell-internally buffered crossbar switch," in Proc. IEEE Global Telecommun. Conf., vol. 7, Dec. 2003, pp. 3688-3693.
-
(2003)
Proc. IEEE Global Telecommun. Conf.
, vol.7
, pp. 3688-3693
-
-
Mhamdi, L.1
Hamdi, M.2
-
27
-
-
0037609302
-
"Output-queued switch emulation by fabrics with limited memory"
-
May
-
R. B. Magill, C. E. Rohrs, and R. L. Stevenson, "Output-queued switch emulation by fabrics with limited memory," IEEE J. Sel. Areas Commun., vol. 21, no. 4, pp. 606-615, May 2003.
-
(2003)
IEEE J. Sel. Areas Commun.
, vol.21
, Issue.4
, pp. 606-615
-
-
Magill, R.B.1
Rohrs, C.E.2
Stevenson, R.L.3
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