Analysis of nonblocking ATM switches with multiple input queues

IEEE/ACM Transactions on Networking

Volumn 7, Issue 1, 1999, Pages 60-74

  Nong, Ge ^a,b   Muppala, Jogesh K ^a,b   Hamdi, Mounir ^a,b  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b IEEE   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL ITERATIVE MATCHING (PIM);

ALGORITHMS; COMPUTER SIMULATION; INTERCONNECTION NETWORKS; ITERATIVE METHODS; MATHEMATICAL MODELS; PROBABILITY; QUEUEING NETWORKS; TELECOMMUNICATION TRAFFIC;

ASYNCHRONOUS TRANSFER MODE;

EID: 0032663268     PISSN: 10636692     EISSN: None     Source Type: Journal    
DOI: 10.1109/90.759320     Document Type: Article

References (25)

1. R. Rooholamini and V. Cherkassky, "Finding the right ATM switch for the market," IEEE Trans. Comput., vol. 27, pp. 16-28, Apr. 1994.
2. R. Y. Awdeh and H. T. Mouftah, "Survey of ATM switch architectures," Computer Networks and ISDN Systems, vol. 27, pp. 1567-1613, 1995.
3. M. Hamdi and J. Muppala, "Performance evaluation of nonblocking ATM switches under various traffic and buffering schemes," Int. J. Commun. Syst., vol. 9, pp. 59-79, 1996.
4. M. Karol, M. Hluchyj, and S. Morgan, "Input versus output queueing on a space division packet switch," IEEE Trans. Commun., vol. 35, pp. 1347-1356, Dec. 1987.
5. A. Pattavina and G. Bruzzi, "Analysis of input and output queueing for nonblocking ATM switches," IEEE/ACM Trans. Networking, vol. 1, pp. 314-328, June 1993.
6. P. Achille and B. Giacomo, "Analysis of input and output queueing for nonblocking ATM switches," ACM Trans. Networking, vol. 1, June 1993.
7. T. E. Anderson, S. S. Owicki, J. B. Saxe, and C. P. Thacker, "High-speed switch scheduling for local-area networks," ACM Trans. Comput. Syst., vol. 11, no. 4, pp. 319-352, Nov. 1993.
8. N. McKeown, M. Izzard, A. Mekkittikul, B. Ellersick, and M. Horowitz, "Tiny tera: A packet switch core," IEEE Micro, vol. 17, pp. 26-33, Jan. 1997.
9. N. W. McKeown, "Scheduling algorithms for input-queued cell switches," Ph.D. dissertation, Univ. California at Berkeley, 1994.
10. N. Mckeown, P. Varaiya, and J. Walrand, "Scheduling cells in an input-queued switch," Electron. Lett., vol. 29, no. 25, pp. 2174-2175, 1993.
11. B. Prabhakar, N. Mckeown, and R. Ahuja, "Multicast scheduling for input-queued switches," IEEE J. Select. Areas Commun., vol. 15, pp. 855-866, June 1997.
12. R. O. LaMaire and D. N. Serpanos, "Two-dimentional round-robin schedulers for packet switches with multiple input queues," IEEE/ACM Trans. Networking, vol. 2, pp. 471-481, Oct. 1994.
13. J. A. Bondy and U. S. R. Murty, Graph Theory with Applications. Amsterdam, The Netherlands: Elsevier, 1976.
14. M. Hamdi, J. Wang, and K. Ben Letaief, "Efficient estimation of cell loss and cell delay on nonblocking ATM switches using importance sampling," presented at GLOBECOM '97.
15. Y. C. Jung and C. K. Un, "Analysis of backpressure-type packet switches with input and output buffering," Proc. Inst. Elect. Eng., vol. 140, Aug. 1993.
16. _, "Performance analysis of packet switches with input and output buffers," Computer Networks and ISDN Systems, vol. 26, pp. 1559-1580, 1994.
17. M. J. Lee and D. S. Ahn, "Cell loss analysis and design trade-offs of nonblocking ATM switches," IEEE/ACM Trans. Networking, vol. 3, pp. 199-210, Apr. 1995.
18. M. K. Mehmet-Ali, M. Youssefi, and H. T. Nguyen, "The performance analysis and implementation of an input access scheme in a high-speed packet switch," IEEE Trans. Commun., vol. 42, pp. 3189-3199, Dec. 1994.
19. M. F. Neuts, Matrix-Geometric Solutions in Stochastic Models. Baltimore, MD: The Johns Hopkins Press, 1981.
20. E. Del Re and R. Fantacci, "Performance evaluation of input and output queueing techniques in ATM switching systems," IEEE Trans. Commun., vol. 41, pp. 1565-1575, Oct. 1993.
21. J. Medhi, Stochastic Models in Queueing Theory. New York: Academic, 1991.
22. M. Abramowitz and I. A. Stegun, Eds., Handbook of Mathematical Functions with Formulas, Graphs, and Mathematical Tables. New York: Wiley, 1972.
23. L. Jacob and A. Kumar, "Saturated throughput analysis of an input queueing ATM switch with multiclass bursty traffic," IEEE Trans. Commun., vol. 43, pp. 757-761, Apr. 1995.
24. X. R. Cao and D. Towsley, "A performance model for ATM switches with general packet length distributions," IEEE/ACM Trans. Networking, vol. 3, pp. 299-309, June 1995.
25. N. McKeown, V. Anantharam, and J. Walrand, "Achieving 100% throughput in an input-queued switch," in Proc. IEEE INFOCOM '96, 1996, vol. 1, pp. 296-302.