10-Gb/s (1.25 Gb/s×8) 4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 12, 1999, Pages 1921-1934

  Oki, Eiji ^a   Yamanaka, Naoaki ^a   Ohtomo, Yusuke ^b   Okazaki, Kazuhiko ^a   Kawano, Ryusuke ^a  

^a NTT Network Service Systems Laboratories   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; COUPLED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRONICS PACKAGING; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; MULTICHIP MODULES;

DISTRIBUTED CONTENTION CONTROL METHOD; PSEUDO-EMITTER-COUPLED LOGICS; SCALABLE DISTRIBUTED ARBITRATION;

CMOS INTEGRATED CIRCUITS;

EID: 0033280278     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.808917     Document Type: Article

References (27)

1. N. Yamanaka, S. Yasukawa, E. Oki, T. Kurimoto, T. Kawamura, and T. Matsumura, "OPTIMA: Tb/s ATM switching system architecture based on highly statistical optical WDM interconnection," in Proc. ISS'97, 1997, p. IS-02.8.
2. E. Munter, J. Parker, and P. Kirkby, "A high-capacity ATM switch based on advanced electronic and optical techniques," IEEE Commun. Mag., pp. 64-71, 1995.
3. H. Ahmadi and W. E. Denzel, "A survey of modern high-performance switching techniques," IEEE J. Select. Areas Commun., vol. 7, no. 7, pp. 1091-1103, 1989.
4. M. G. Hluchyj and M. J. Karol, "Queueing in high-performance packet switching," IEEE J. Select. Areas Commun., vol. 6, no. 9, pp. 1587-1597, 1988.
5. Y. Oie, T. Suda, M. Murata, D. Kolson, and H. Miyahara, "Survey of switching techniques in high-speed networks and their performance," in Proc. IEEE Infocom'90, pp. 1242-1251.
6. Y. S. Yeh, M. G. Hluchyj, and A. S. Acampora, "The knockout switch; A simple, modular, architecture for high-performance packet switching," in Proc. ISS'87, 1987, vol. B10.2.1, pp. 801-808.
7. H. J. Chao, B.-S. Choe, J.-S. Park, and N. Uzun, "Design and implementation of Abacus switch: A scalable multicast ATM switch," IEEE J. Select. Areas Commun., vol. 15, no. 5, pp. 830-843, 1997.
8. I. Iliadis and W. E. Denzel, "Analysis of packet switches with input and output queueing," IEEE Trans. Commun., vol. 41, no. 5, pp. 731-740, 1993.
9. Y. Oie, M. Murata, K. Kubota, and H. Miyahara, "Effect of speedup in nonblocking packet switch," in Proc. ICC89, 1989, p. 410.
10. N. Yamanaka, K. Endo, K. Genda, H. Fukuda, T. Kishimoto, and S. Sasaki, "320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM," IEEE Trans. Comp., Packag., Manufact. Technol., vol. 18, pp. 83-91, 1995.
11. M. J. Karol, M. G. Hluchyj, and S. P. Morgan, "Input versus output queueing on a space-division packet switch," IEEE Trans. Commun., vol. COM-35, pp. 1347-1356, 1987.
12. M. J. Karol, K. Y. Eng, and H. Obara, "Improving the performance of input-queued ATM packet switches," in Proc. IEEE Infocom'92, 1992, pp. 110-115.
13. N. Mackeown, "Scheduling algorithm for input-queued cell switches," Ph.D. dissertation, University of California at Berkeley, 1995.
14. H. Tomonaga, N. Matsuoka, Y. Kato, and Y. Watanabe, "High-speed switching module for a large capacity ATM switching system," in Proc. IEEE GLOBECOM'92, 1992, pp. 123-127.
15. K. Genda, Y. Doi, K. Endo, T. Kawamura, and S. Sasaki, "A 160-Gb/s ATM switching system using an internal speed-up crossbar switch," in Proc. IEEE GLOBECOM'94, 1994, pp. 123-133.
16. E. Oki, N. Yamanaka, and Y. Ohtomo, "A 10 Gb/s (1.25 Gb/s × 8) 4 × 2 CMOS/SIMOX ATM switch," in IEEE ISSCC99, Feb. 1999, pp. 172-173.
17. E. Oki and N. Yamanaka, "Scalable crosspoint buffering ATM switch architecture using distributed arbitration scheme," in Proc. IEEE ATM'97 Workshop, 1997, pp. 28-35.
18. A. Cisneros and C. A. Brackett, "A large ATM switch based on memory switches and optical star couplers," IEEE J. Select. Areas Commun., vol. 9, no. 8, pp. 1348-1360, 1991.
19. Y. Ohtomo, M. Nogawa, and M. Ino, "A 2.6-Gbps/pin SIMOX-CMOS low-voltage-swing interface circuit," IEICE Trans. Electron., vol. E79-C, no. 4, pp. 524-529, 1996.
20. S. Yasuda, Y. Ohtomo, M. Ino, Y. Kado, and T. Tsuchiya, "3-Gb/s CMOS 1:4 MUX and DEMUX IC's," IEICE Trans. Electron., vol. E78-C, no. 12, pp. 1746-1753, 1995.
21. Y. Ohtomo, S. Yasuda, M. Nogawa, J. Inoue, K. Yamakoshi, H. Sawada, M. Ino, S. Hino, Y. Sato, Y. Takei, T. Watanabe, and K. Takeya, "A 40 Gb/s 8 × 8 ATM switch LSI using 0.25 μm CMOS/SIMOX," in Proc. IEEE ISSCC97, 1997, pp. 154-155.
22. E. Oki and N. Yamanaka, "High-speed tandem-crosspoint ATM switch architecture with input and output buffers," IEICE Trans. Commun., vol. E81-B, no. 2, pp. 215-223, 1998.
23. M. Ino, "Low-power and high-speed LSI's using 0.25 μm CMOS/SIMOX," IEICE Trans. Electron., vol. E80-C, no. 12, 1997.
24. Y. Tsukada, "Bare chip packaging technology," in Proc. Advances in Electronic Packaging Conf., 1997, vol. 1, pp. 285-290.
25. K. Okazaki, N. Sugiura, A. Harada, N. Yamanaka and E. Oki, "80-Gbit/s MCM-C technologies for high-speed ATM switching systems," in Proc. IMAPS Int. Conf. Exhibition High Density Packaging & MCMs, Apr. 1999, pp. 284-288.
26. T. Sakai, S. Konaka, Y. Kobayashi, M. Suzuki, and Y. Kawai, "Gigabit logic bipolar technology: Advanced super self-aligned process technology," Electron. Lett., vol. 19, pp. 283-234, 1983.
27. S. Sasaki, T. Kishimoto, K. Genda, K. Endo, and K. Kaizu, "Multichip module technologies for high-speed ATM switching Systems," in Proc. '94 MCM Conf., 1994, pp. 130-135.