The HIMOS flash technology: The alternative solution for low-cost embedded memory

Proceedings of the IEEE

Volumn 91, Issue 4, 2003, Pages 627-634

  Van Houdt, Jan ^a,b   Wellekens, Dirk ^b   Haspeslagh, Luc ^b  

^a IEEE   (Belgium)

^b IMEC   (Belgium)

Author keywords

Embedded nonvolatile memory; Flash electrically erasable programmable ROM (EEPROM); High injection MOS (HIMOS); Source side injection

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; EMBEDDED SYSTEMS; FLASH MEMORY; LOGIC DESIGN; PROM;

EMBEDDED NONVOLATILE MEMORY; FLASH ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM); HIGH-INJECTION MOS (HIMOS); SOURCE-SIDE INJECTION;

MOS DEVICES;

EID: 4544272065     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.811715     Document Type: Review

References (17)

1. L. Baldi and A. Maurelli, "Embedded nonvolatile memories in deep-submicron CMOS," in Proc. ESSDERC, H. E. Macs, R. P. Mertens, G. Declerck, and H. Grünbacher, Eds., 1999, pp. 127-134.
2. J. Van Houdt, G. Groeseneken, and H. E. Maes, "Method for programming a semiconductor memory device," "Transistor structure for use in erasable and programmable semiconductor memory devices," U.S. patents 5 583 810 and 5 583 811, Dec. 10, 1996.
3. 2PROM cell for embedded memory applications," IEEE Trans. Electron Devices, vol. 40, pp. 2255-2263, Dec. 1993.
4. J. Van Houdt, D. Wellekens, L. Faraone, L. Haspeslagh, L. Deferm, G. Groeseneken, and H. E. Maes, "A 5 V-compatible Flash EEPROM cell with microsecond programming time for embedded memory applications," IEEE Trans. Comp., Packag., Manuf. Technol. A, vol. 17, pp. 380-389, Sept. 1994.
5. 2PROM," in VLSI Tech. Symp., 1994, pp. 71-72.
6. J. Van Houdt, P. Heremans, L. Deferm, G. Groeseneken, and H. E. Maes, "Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications," IEEE Trans. Electron Devices, vol. 39, pp. 1150-1156, May 1992.
7. J. Van Houdt, L. Haspeslagh, D. Wellekens, G. Vanhorebeek, G. Groeseneken, L. Deferm, and H. E. Maes, "A 25 ns/byte-programmable low-power SSI Flash array with a new low-voltage erase scheme for embedded memory applications," in Proc. 14th IEEE Nonvolatile Semiconductor Memory Workshop, 1995, p. 2.
8. D. -S. Kuo et al., "A foundry operation with Flash technology," in Proc. 17th IEEE Nonvolatile Semiconductor Memory Workshop, 2000, pp. 14-21.
9. J. Van Houdt, G. Groeseneken, and H. E. Maes, "Contactless array configuration for semiconductor memories," U.S. Patent 6 009 013, Dec. 28, 1999.
10. J. Tsouhlarakis, G. Vanhorebeek, G. Verhoeven, J. De Blauwe, S. Kim, D. Wellekens, P. Hendrickx, L. Haspeslagh, J. Van Houdt, and H. Maes, "A Flash memory technology with quasivirtual ground array for low-cost embedded applications," IEEE J. Solid-State Circuits, vol. 6, pp. 969-978, June 2001.
11. J. Van Houdt, L. Haspeslagh, L. Deferm, G. Groeseneken, and H. E. Maes, "Method of programming a Flash EEPROM memory cell array optimized for low power consumption," U.S. Patent 6 044 015, Mar. 28, 2000.
12. D. Wellekens, J. Van Houdt, L. Faraone, G. Groeseneken, and H. E. Maes, "Write/erase degradation in source side injection Flash EEPROM's: Characterization techniques and wearout mechanisms," IEEE Trans. Electron Devices., vol. 42, pp. 1992-1998, Nov. 1995.
13. J. De Blauwe, J. Van Houdt, D. Wellekens, G. Groeseneken, and H. E. Maes, "SILC-related effects in Flash EEPROM's - Part II: Prediction of steady-state SILC-related disturb characteristics," IEEE Trans. Electron Devices, vol. 45, pp. 1751-1760, Aug. 1998.
14. R. Degraeve, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. Van Houdt, L. Haspeslagh, G. Groeseneken, and G. Tempel, "Analytical model for failure rate prediction due to anomalous charge loss of Flash memories," in Int. Electron Devices Meeting Tech. Dig., 2001, pp. 699-702.
15. D. Wellekens, "Radiation and reliability aspects of electrically erasable floating gate memory devices," Ph.D. dissertation, Katholieke Univ. Leuven, Leuven, Belgium, 1995.
16. D. K. Y. Liu, C. Kaya, M. Wong, J. Paterson, and P. Shah, "Optimization of a source-side-injection FAMOS cell for Flash EPROM applications," IEDM Tech. Dig., pp. 315-318, 1991.
17. J. Van Houdt, D. Wellekens, G. Groeseneken, and H. E. Maes, "Investigation of the soft-write mechanism in source-side injection Flash EEPROM devices," IEEE Electron Device Lett., vol. 16, pp. 181-183, May 1995.