Reliability investigation upon 30nm gate length ultra-high aspect ratio FinFETs

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2005, Pages 541-544

  Liao, Wen Shiang ^a   Chen, Shiao Shien ^a   Chiang, Sinclair ^a   Shiau, Wei Tsun ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

FinFET; HCI; High aspect ratio; NBTI; Q bd; Vbd; Vertical double gate

Indexed keywords

FINFET; HIGH ASPECT RATIO; NBTI; QBD; VBD; VERTICAL DOUBLE GATE;

ASPECT RATIO; HUMAN COMPUTER INTERACTION; MOS DEVICES; NITRIDES; RELIABILITY; ROBUSTNESS (CONTROL SYSTEMS);

FIELD EFFECT TRANSISTORS;

EID: 28744442985     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, "A folded-channel MOSFET for deep-sub-tenth micron Era," in IEDM Tech. Dig., 1998, pp. 1032-1034.
2. J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.-S. P. Wong, "Extension and source/drain design for high-performance FinFET devices," IEEE-ED, vol. 50, no. 4, pp. 952-958, 2003.
3. B. Yu, L. Chang, S.Ahmed, H. Wang, S. Bell, C.-Y Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Boker, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10n
4. F. -L. Yang, H.-Y. Chen, F.-C. Chen, Y.-L-.Chan, K.-N. Yang, C.-J. Chen, H.-J. Tao, Y.-K. Choi, M.-S. Liang, C. Hu, "35nm CMOS FinFETs," in VLSI Tech. Dig., 2002, pp. 104-105.
5. t asymmetric-gate FinFET devices," in IEDM Tech. Dig. 2001, pp. 437-440.
6. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Boker, and C. Hu, "Sub-20nm CMOS FinFET technologies," in IEDM Tech. Dig., 2001, pp. 421-424.
7. Y.-K. Choi, D. Ha, E. Snow, J. Bokor, and T.-J. King, "Reliability Study of CMOS FinFETs," in IEDM Tech. Dig., 2003, pp. 7.6.1-7.6.4.
8. M. A. Alam, B. E. Weir, and P. J. Silverman, "A study of soft and hard breakdown - Part II: Principles of area, thickness, and voltage scaling," IEEE-ED, 2002, v.49, pp. 239-246.
9. S. Mahapatra, P. B. Kumar, and M. A. Alam, "Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs," IEEE-ED, 2004, v.51, pp. 1371-1379.