Design methodologies and circuit design trade-offs for the HP PA 8000 processor

Hewlett-Packard Journal

Volumn 48, Issue 4, 1997, Pages 16-21

  Dorweiler, Paul J ^a   Moore, Floyd E ^a   Josephson, D Douglas ^a   Colon Bonet, Glenn T ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; ELECTRONICS PACKAGING; FLIP FLOP CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS; SIGNAL NOISE MEASUREMENT; TIMING CIRCUITS;

CROSS CHIP SIGNAL INTEGRITY;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0031208259     PISSN: 00181153     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (0)