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Volumn , Issue , 2005, Pages 3-11

Defects, yield, and design in sublithographic nano-electronics

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKS; DESIGN AUTOMATION; MOLECULAR CROSSBARS; TOLERANT FLOW;

EID: 28444440223     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (34)

References (14)
  • 1
    • 0035834444 scopus 로고    scopus 로고
    • Logic circuits with carbon nanotube transistors
    • A. Bachtold, P. Harley, T. Nakanishi, C. Dekker, "Logic Circuits with Carbon Nanotube Transistors" Science, vol. 294, pp 1317-1320, 2001.
    • (2001) Science , vol.294 , pp. 1317-1320
    • Bachtold, A.1    Harley, P.2    Nakanishi, T.3    Dekker, C.4
  • 5
    • 0035793378 scopus 로고    scopus 로고
    • Functional nanoscale electronics devices assembled using silicon nanowire building blocks
    • Y. Cui, C. M. Lieber, "Functional Nanoscale Electronics Devices Assembled Using Silicon Nanowire Building Blocks", Science, vol 291, pp. 851-853, 2001.
    • (2001) Science , vol.291 , pp. 851-853
    • Cui, Y.1    Lieber, C.M.2
  • 7
    • 0141499770 scopus 로고    scopus 로고
    • Array-based architecture for FET-based, nanoscale electronics
    • A. DeHon, "Array-Based Architecture for FET-Based, Nanoscale Electronics", IEEE Trans. on Nanotechnology, vol 2, No. 1, pp. 23-32, 2003.
    • (2003) IEEE Trans. on Nanotechnology , vol.2 , Issue.1 , pp. 23-32
    • DeHon, A.1
  • 10
    • 0035834415 scopus 로고    scopus 로고
    • Logic gates and computation from assembled nanowire building blocks
    • Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K. H. Kim, C. M. Lieber, "Logic Gates and Computation From Assembled Nanowire Building Blocks", Science, vol 294, pp. 1313-1317, 2001.
    • (2001) Science , vol.294 , pp. 1313-1317
    • Huang, Y.1    Duan, X.2    Cui, Y.3    Lauhon, L.J.4    Kim, K.H.5    Lieber, C.M.6
  • 11
    • 0015960393 scopus 로고
    • Testing for faults in wiring networks
    • W. H. Kautz, "Testing for Faults in Wiring Networks", IEEE Trans. On Computers, vol. C-23, No. 4, pp. 358-363, 1974.
    • (1974) IEEE Trans. on Computers , vol.C-23 , Issue.4 , pp. 358-363
    • Kautz, W.H.1
  • 13
    • 34250888250 scopus 로고
    • Modeling defect spatial distribution
    • F. J. Meyer, D. K. Pradhan, "Modeling Defect Spatial Distribution", IEEE Trans. on Computers, Vol. 38, No. 4, pp. 538-546, 1989.
    • (1989) IEEE Trans. on Computers , vol.38 , Issue.4 , pp. 538-546
    • Meyer, F.J.1    Pradhan, D.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.