-
1
-
-
4143090909
-
Electronic textiles: A platform for pervasive computing
-
December
-
D. Marculescu et al., Electronic Textiles: A Platform for Pervasive Computing, Proceedings of the IEEE, Vol. 91, No 12, pp. 1995-2018, December 2003.
-
(2003)
Proceedings of the IEEE
, vol.91
, Issue.12
, pp. 1995-2018
-
-
Marculescu, D.1
-
3
-
-
0036565392
-
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters
-
May
-
B.A. Floyd, Hung Chih-Ming; K.K O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters", IEEE Journal of Solid-State Circuits, Vol. 37, No 5, pp. 543-552, May 2002.
-
(2002)
IEEE Journal of Solid-state Circuits
, vol.37
, Issue.5
, pp. 543-552
-
-
Floyd, B.A.1
Chih-Ming, H.2
O, K.K.3
-
4
-
-
4344668572
-
WiseNET: An ultralow-power wireless sensor network solution
-
August
-
C. C. Enz, A. El-Hoiydi, J. Decotignie, V. Peiris, "WiseNET: An ultralow-power wireless sensor network solution", IEEE Computer, Vol. 37, Nr. 8, pp. 62-70, August 2004.
-
(2004)
IEEE Computer
, vol.37
, Issue.8
, pp. 62-70
-
-
Enz, C.C.1
El-Hoiydi, A.2
Decotignie, J.3
Peiris, V.4
-
5
-
-
2442607953
-
A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications
-
May
-
S. Cho, A. P. Chadrakasan, "A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications", IEEE Journal of Solid-State Circuits, Vol. 39, No 5, pp. 731-738, May 2004.
-
(2004)
IEEE Journal of Solid-state Circuits
, vol.39
, Issue.5
, pp. 731-738
-
-
Cho, S.1
Chadrakasan, A.P.2
-
6
-
-
16544368640
-
A 1-V CMOS SOI bluetooth RF transceiver using LC-tuned and transistor-current-source folded circuits
-
April
-
M. Ugajin, A. Yamagishi, J. Kodate, M. Harada, T. Tsukahara, "A 1-V CMOS SOI Bluetooth RF Transceiver Using LC-Tuned and Transistor-Current-Source Folded Circuits", IEEE Journal of Solid-State Circuits, Vol. 39, No 4, pp. 569-576, April 2004.
-
(2004)
IEEE Journal of Solid-state Circuits
, vol.39
, Issue.4
, pp. 569-576
-
-
Ugajin, M.1
Yamagishi, A.2
Kodate, J.3
Harada, M.4
Tsukahara, T.5
-
7
-
-
0031147079
-
A 1.5-V, 1.5-GHz CMOS low noise amplifier
-
May
-
D. Shaeffer, T. Lee, "A 1.5-V, 1.5-GHz CMOS low noise amplifier", IEEE Journal of Solid-State Circuits, Vol. 32, No 5, pp. 745-759, May 1997.
-
(1997)
IEEE Journal of Solid-state Circuits
, vol.32
, Issue.5
, pp. 745-759
-
-
Shaeffer, D.1
Lee, T.2
-
8
-
-
3042612303
-
2.4 GHz high gain low power narrowband low-noise amplifier (LNA) in 0.18 um TSMC CMOS
-
E. Kunz, S. Parke, "2.4 GHz high gain low power narrowband low-noise amplifier (LNA) in 0.18 um TSMC CMOS", in Workshop on Microelectronics and Electron Devices, 2004, pp. 52-54.
-
(2004)
Workshop on Microelectronics and Electron Devices
, pp. 52-54
-
-
Kunz, E.1
Parke, S.2
-
9
-
-
0029244247
-
Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS
-
February
-
B. Razavi, K. Lee, R. Yan, "Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS", IEEE Journal of Solid-State Circuits, Vol. 30, No 2, pp. 101-108, February 1995.
-
(1995)
IEEE Journal of Solid-state Circuits
, vol.30
, Issue.2
, pp. 101-108
-
-
Razavi, B.1
Lee, K.2
Yan, R.3
-
10
-
-
0024611252
-
High speed CMOS circuit technique
-
February
-
J. Yuan, C Svensson, "High speed CMOS circuit technique", IEEE Journal of Solid-State Circuits, Vol. 24, No 2, pp. 62-70. February 1989.
-
(1989)
IEEE Journal of Solid-state Circuits
, vol.24
, Issue.2
, pp. 62-70
-
-
Yuan, J.1
Svensson, C.2
-
11
-
-
1242288219
-
A 13.5 mW 5-GHz frequency synthesizer with dynamic-logic frequency divider
-
February
-
S. Pellerano, S. Levantine, C. Samori, A. Lacaita, "A 13.5 mW 5-GHz frequency synthesizer with dynamic-logic frequency divider", IEEE Journal of Solid-State Circuits, Vol. 39, No 2, pp. 378-383, February 2004.
-
(2004)
IEEE Journal of Solid-state Circuits
, vol.39
, Issue.2
, pp. 378-383
-
-
Pellerano, S.1
Levantine, S.2
Samori, C.3
Lacaita, A.4
-
12
-
-
0030107330
-
Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase-clock
-
March
-
Q. Huang, R. Rogenmoser, "Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase-clock", IEEE Journal of Solid-State Circuits, Vol. 31, No 3, pp. 456-465, March 1996.
-
(1996)
IEEE Journal of Solid-state Circuits
, vol.31
, Issue.3
, pp. 456-465
-
-
Huang, Q.1
Rogenmoser, R.2
-
13
-
-
0019079092
-
Charge pump PLL
-
November
-
F. Gardner, "Charge Pump PLL", IEEE Transactions on Communications, Vol. 28, No 11, pp. 1849-1859, November 1980.
-
(1980)
IEEE Transactions on Communications
, vol.28
, Issue.11
, pp. 1849-1859
-
-
Gardner, F.1
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