BitSNAP: Dynamic significance compression for a low-energy sensor network asynchronous processor

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2005, Pages 144-154

  Ekanayake, Virantha N ^a   Kelly IV, Clinton ^a   Manohar, Rajit ^a  

^a Department of Molecular Biology and Genetics   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ENERGY UTILIZATION; SENSORS;

ASYNCHRONOUS PROCESSOR ARCHITECTURE; SENSOR NETWORK ASYNCHRONOUS PROCESSOR (SNAP);

MICROPROCESSOR CHIPS;

EID: 28444433770     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2005.14     Document Type: Conference Paper

References (21)

1. Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor-Network Asynchronous Processor. In Proc. International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2003.
2. Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An ultra low-power processor for sensor networks. In Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004.
3. P. Levis et al. The emergence of networking abstractions and techniques in TinyOS. In Proceedings of the First USENIX/ACM Symposium on Networked Systems Design and Implementation (NSDI), 2004.
4. J. Hill et al. System architecture directions for network sensors. In Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2000.
5. R. Canal, A. González, and J.E. Smith. Very Low Power Pipelines using Significance Compression. In Proc. International Symposium on Microarchitecture, December 2000.
6. Rajit Manohar. Width-Adaptive Data Word Architectures. In Proc. International Conference on Advanced Research in VLSI, March 2001.
7. D. Brooks and M. Martonosi. Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. In Proc. International Symposium on High-Performance Computer Architecture (HPCA), 1999.
8. D. Fang and R. Manohar. Non-uniform access asynchronous register files. In Proc. International Symposium on Asynchronous Circuits and Systems (ASYNC), Apr 2004.
9. P. B. Denyer and David Renshaw. VLSI Signal Processing; A Bit-Serial Approach. Addison-Wesley Longman Publishing Co., Inc., 1985.
10. Richard I. Hartley and Peter F. Corbett. A digit-serial silicon compiler. In Proceedings of the 25th ACM/IEEE conference on Design automation, pages 646-649. IEEE Computer Society Press, 1988.
11. Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nystroem, Paul Penzes, Robert Southworth, and Uri Cummings. The design of an asynchronous MIPS R3000 microprocessor In Advanced Research in VLSI, pages 164-181, 1997.
12. Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, and Pieter J. Hazewindus. The design of an asynchronous microprocessor. In Charles L. Seitz, editor, Proc. International Conference on Advanced Research in VLSI, pages 351-373, 1991.
13. M. Renaudin, P. Vivet, and F. Robin. ASPRO-216: A standard-cell QDI 16-bit RISC asynchronous microprocessr. In 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), pages 22-32, 1998.
14. S. B. Furber, D. A. Edwards, and J. D. Garside. AMULET3: a 100 MIPS asynchronous embedded processor. In Proc. International Conf. Computer Design (ICCD), 2000.
15. Alain J. Martin, Mika Nystrm, and Catherine G. Wong. Three generations of asynchronous microprocessors. IEEE Design and Test of Computers, special issue on Clockless VLSI Design, Nov/Dec 2003.
16. Hans van Gageldonk, Kees van Berkel, Ad Peeters, Daniel Baumann, Daniel Gloor, and Gerhard Stegmann. An asynchronous low-power 80c51 microcontroller. In ASYNC '98: Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems, page 0096. IEEE Computer Society, 1998.
17. Luis Villa, Michael Zhang, and Krste Asanovic. Dynamic zero compression for cache energy reduction. In Proc. International Symposium on Microarchitecture, Dec 2000.
18. Nam Sung Kim, Todd Austin, and Trevor Mudge. Low-energy data cache using sign compression and cache line bisection. In 2nd Annual Workshop on Memory Performance Issues, May 2002.
19. Lars S. Nielsen and Jens Sparsø. Designing asynchronous circuits for low power: An IFIR filter bank for a digital hearing aid. Proceedings of the IEEE, 87(2):268-281, February 1999.
20. C.A.R. Hoare. Communicating sequential processes. Communications of the ACM, pages 666-677, 1978.
21. Alain J. Martin. Synthesis of asynchronous VLSI circuits. In J. Straunstrup, editor, Formal Methods for VLSI Design, pages 237-283. North-Holland, 1990.