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Volumn , Issue , 2001, Pages 112-129

Width-adaptive data word architectures

Author keywords

Adders; Algorithm design and analysis; Circuit simulation; Computer architecture; Delay; Energy efficiency; Laboratories; Power engineering and energy; Throughput; Very large scale integration

Indexed keywords

ADDERS; CIRCUIT SIMULATION; ENERGY EFFICIENCY; LABORATORIES; THROUGHPUT; VLSI CIRCUITS;

EID: 0038788423     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.2001.915555     Document Type: Conference Paper
Times cited : (11)

References (21)
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    • Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, Caltech Computer Science Technical Report CS-TR-98-12, July 1998.
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    • Manohar, R.1
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    • Slack Elasticity in Concurrent Computing
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    • Manohar, R.1    Martin, A.J.2
  • 12
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    • Rajit Manohar and José Tierno. Asynchronous Parallel Prefix Computation. IEEE Transactions on Computers 47(11):1244-1252. November 1998.
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    • Manohar, R.1    Tierno, J.2
  • 13
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    • Formal Program Transformations for VLSI Circuit Synthesis
    • E.W. Dijkstra, editor, Formal Development of Programs and Proofs, Addison Wesley
    • Alain J. Martin. Formal Program Transformations for VLSI Circuit Synthesis. In E.W. Dijkstra, editor, Formal Development of Programs and Proofs, UT Year of Programming Series, pp. 59-80, Addison Wesley, 1989.
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    • Martin, A.J.1
  • 14
    • 0022879965 scopus 로고
    • Compiling Communicating Processes into Delay-insensitive VLSI circuits
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.