Power optimisation of FPGA-based designs without rewiring

IEE Proceedings: Computers and Digital Techniques

Volumn 147, Issue 3, 2000, Pages 167-174

  Kumthekar, B ^a   Benini, L ^a   Macii, E ^b   Somenzi, F ^c  

^a UCB 450   (United States)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC PROGRAMMING; TABLE LOOKUP;

CONFIGURABLE LOGIC BLOCKS (CLB); POWER-ORIENTED RECONFIGURATION SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034187956     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20000497     Document Type: Article

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