Distributed data-retention power gating techniques for column and row Co-controlled embedded SRAM

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2005, Pages 129-134

  Hua, Chung Hsien ^a   Cheng, Tung Shuan ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COLUMN DECODERS; DISTRIBUTED DATA-RETENTION POWER GATING TECHNIQUES; EMBEDDED MEMORIES;

ACOUSTIC NOISE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA ACQUISITION; DECODING;

STATIC RANDOM ACCESS STORAGE;

EID: 28344448848     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2005.21     Document Type: Conference Paper

References (7)

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3. M. Anis, S. Areibi, and M. Elmasry, "Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, issue 10, pp. 1324-1342, Oct. 2003.
4. th International Symposium on Quality Electronics Design, March 2004, pp. 55-60.
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6. t Low-Leakage Gated-Ground Cache for Deep Submicron," IEEE Journal of Solid-State Circuits, vol. 38, pp. 319-328, Feb. 2003.
7. 2 8T-Thin Cell Using Dynamically-Controlled Column Bias Scheme," in International Solid-State Circuits Conference Dig. Tech. Papers, Feb. 2004, pp. 508-509.