Semiconductor PN junction failure at operation near or in the breakdown region of the reverse I-V characteristic

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2005, Pages 200-204

  Obreja, V V N ^a,b   Codreanu, C ^a,b   Poenar, D ^d   Buiu, O ^c  

^a NATIONAL INSTITUTE FOR RESEARCH AND DEVELOPMENT IN MICROTECHNOLOGIES   (Romania)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c UNIVERSITY OF LIVERPOOL   (United Kingdom)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28044436244     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. W. Wondrak, "Physical limits and lifetime limitations of semiconductor devices at high temperature", Microelectronics Reliability, vol.39, pp.1113-1120, 1999
3. A. Czerwinski, E. Simoen, A. Poyai, C. Claeys, "Peripheral current analysis of silicon p-n junction and gated diodes" J. Appl. Phys.,vol.88, no.11, pp. 6506-6514, 2000
4. V.V.N. Obreja, "On the leakage current of present-day manufactured semiconductor junctions", Solid-State Electronics, vol.49, no.1, pp. 49-57, 2000
5. V.V.N. Obreja, "An experimental investigation on the nature of reverse current of power silicon PN junctions", IEEE Trans. Electron Devices, vol. ED-49, pp. 155-163, 2002
6. V.V.N. Obreja, "Investigation on operation of silicon power devices in the breakdown region of electrical characteristic", in Proc. International Semiconductor Conference (CAS2001), 2001, p.485
7. th Int. Conf.on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems (EuroSIME 2005), 2005, p. 584
8. V.V.N. Obreja, "Influence of PN junction surface region upon the peak pulse power of silicon transient voltage suppressors" in Proc. International Semiconductor Conference (CAS1997), 1997, p. 331