-
1
-
-
0029510949
-
An experimental chip to evaluate test techniques experiment results
-
S. C. Ma, P. Franco and E. J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results", in Proc. Intl. Test Conf., 1995, pp. 663-672.
-
(1995)
Proc. Intl. Test Conf.
, pp. 663-672
-
-
Ma, S.C.1
Franco, P.2
McCluskey, E.J.3
-
2
-
-
0029215035
-
On the decline of testing efficiency as the fault coverage approaches 100%
-
April
-
L.-C. Wang, M. R. Mercer and T. W. Williams, "On the Decline of Testing Efficiency as the Fault Coverage Approaches 100%", in Proc. VLSI Test Symp., April 1995, pp. 74-83.
-
(1995)
Proc. VLSI Test Symp.
, pp. 74-83
-
-
Wang, L.-C.1
Mercer, M.R.2
Williams, T.W.3
-
4
-
-
0032307602
-
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
-
J. T.-Y. Chang, C.-W. Tseng, C.-M. J. Li, M. Purtell and E. J. McCluskey, "Analysis of Pattern-Dependent and Timing-Dependent Failures in an Experimental Test Chip", in Proc. Intl. Test Conf., 1998, pp. 184-193.
-
(1998)
Proc. Intl. Test Conf.
, pp. 184-193
-
-
Chang, J.T.-Y.1
Tseng, C.-W.2
Li, C.-M.J.3
Purtell, M.4
McCluskey, E.J.5
-
5
-
-
0032184442
-
Test sequences to achieve high defect coverage for synchronous sequential circuits
-
Oct.
-
I. Pomeranz and S. M. Reddy, "Test Sequences to Achieve High Defect Coverage for Synchronous Sequential Circuits", IEEE Trans. on Computer-Aided Design, Oct. 1998, pp. 1017-1029.
-
(1998)
IEEE Trans. on Computer-aided Design
, pp. 1017-1029
-
-
Pomeranz, I.1
Reddy, S.M.2
-
6
-
-
0032638329
-
REDO - Random excitation and deterministic observation - First commercial experiment
-
M. R. Grimaila, S. Lee et. al., "REDO - Random Excitation and Deterministic Observation - First Commercial Experiment", in Proc. VLSI Test Symp., 1999, pp. 268-274.
-
(1999)
Proc. VLSI Test Symp.
, pp. 268-274
-
-
Grimaila, M.R.1
Lee, S.2
-
7
-
-
0035684196
-
Multiple-output propagation transition fault test
-
C.-W. Tseng and E. J. McCluskey, "Multiple-Output Propagation Transition Fault Test", in Proc. Intl. Test Conf., 2001, pp. 358-366.
-
(2001)
Proc. Intl. Test Conf.
, pp. 358-366
-
-
Tseng, C.-W.1
McCluskey, E.J.2
-
8
-
-
0142184749
-
Impact of multiple-detect test patterns on product quality
-
Sept.
-
B. Benware, C. Schuermyer, N. Tamarapalli, K.-H. Tsai, S. Ranganathan, R. Madge, J. Rajski and P. Krishnamurthy, "Impact of multiple-detect test patterns on product quality", in Proc. Intl. Test Conf., Sept. 2003, pp. 1031-1040.
-
(2003)
Proc. Intl. Test Conf.
, pp. 1031-1040
-
-
Benware, B.1
Schuermyer, C.2
Tamarapalli, N.3
Tsai, K.-H.4
Ranganathan, S.5
Madge, R.6
Rajski, J.7
Krishnamurthy, P.8
-
9
-
-
3142752873
-
An experimental stud of n -detect scan ATPG patterns on a processor
-
April
-
S. Venkataraman, S. Sivaraj, E. Amyeen, S. Lee, A Ojha and R. Guo, "An Experimental Stud of n -Detect Scan ATPG Patterns on a Processor", in Proc. 22nd VLSI Test Symp., April 2004, pp. 23-28.
-
(2004)
Proc. 22nd VLSI Test Symp.
, pp. 23-28
-
-
Venkataraman, S.1
Sivaraj, S.2
Amyeen, E.3
Lee, S.4
Ojha, A.5
Guo, R.6
-
10
-
-
8344240295
-
A new approach to test generation and test compaction for scan circuits
-
March
-
I. Pomeranz and S. M. Reddy, "A New Approach to Test Generation and Test Compaction for Scan Circuits", in Proc. Design Automation and Test in Europe Conf., March 2003, pp. 1000-1005.
-
(2003)
Proc. Design Automation and Test in Europe Conf.
, pp. 1000-1005
-
-
Pomeranz, I.1
Reddy, S.M.2
-
11
-
-
0344119472
-
Automatic generation of critical-path tests for a partial-scan microprocessor
-
Oct.
-
J. Grodstein, D. Bhavsar, V. Bettada and R. Davies, "Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor", in Proc. Intl. Conf. on Computer Design, Oct. 2003, pp. 180-186.
-
(2003)
Proc. Intl. Conf. on Computer Design
, pp. 180-186
-
-
Grodstein, J.1
Bhavsar, D.2
Bettada, V.3
Davies, R.4
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