A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 11, 2005, Pages 2296-2302

  Iida, Masahisa ^b,d   Kuroda, Naoki ^b   Otsuka, Hidefumi ^b   Hirose, Masanobu ^b   Yamasaki, Yuji ^b   Ohta, Kiyoto ^b   Shimakawa, Kazuhiko ^b   Nakabayashi, Takashi ^b,e   Yamauchi, Hiroyuki ^a,b   Sano, Tomohiko ^c   Gyohten, Takayuki ^c   Maruta, Masanao ^c   Yamazaki, Akira ^c   Morishita, Fukashi ^c   Dosaka, Katsumi ^c,f   Takeuchi, Masahiko ^c   Arimoto, Kazutami ^a,c,f,g,h  

^a IEEE

^b PANASONIC CORPORATION   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

^d Corporate Semiconductor Division ^*  (Japan)

^e ULSI Process Technology Development Center   (Japan)

^f Institute of Electronics   (Japan)

^g MITSUBISHI ELECTRIC CORPORATION   (Japan)

^h I and M Group

Author keywords

DRAM; Logic compatibility; Low power; Noise cancel; Tuning; Twisted bit line

Indexed keywords

LOGIC COMPATIBILITY; LOW POWER; NOISE CANCEL; TWISTED BIT-LINE;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; NATURAL FREQUENCIES; SPURIOUS SIGNAL NOISE; TUNING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 27844528806     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.857358     Document Type: Article

References (11)

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